• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.2
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• pp.149-156
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• 2011

In the recent years, power analysis attacks were widely investigated, and so various countermeasures have been proposed. In the case of block ciphers, masking methods that blind the intermediate values in the en/decryption computations are well-known among these countermeasures. But the cost of non-linear part is extremely high in the masking method of block cipher, and so the countermeasure for S-box must be efficiently constructed in the case of AES, ARIA and SEED. Existing countermeasures for S-box use the masked S-box table to require 256 bytes RAM corresponding to one S-box. But, the usage of the these countermeasures is not adequate in the lightweight security devices having the small size of RAM. In this paper, we propose the new countermeasure not using the masked S-box table to make up for this weak point. Also, the new countermeasure reduces time-complexity as well as the usage of RAM because this does not consume the time for generating masked S-box table.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.5
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• pp.59-69
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• 2011

Since power analysis attack which uses a characteristic that power consumed by crypto device depends on processed data has been proposed, many logics that can block these correlation originally have been developed. DRP logic has been adopted by most of logics maintains power consumption balanced and reduces correlation between processed data and power consumption. However, semi-custom design is necessary because recently design circuits become more complex than before. This design method causes unbalanced design pattern that makes DRP logic consumes unbalanced power consumption which is vulnerable to power analysis attack. In this paper, we have developed new logic style which adds another discharge phase to discharge two output nodes at the same time based on DyCML to remove this unbalanced power consumption. Also, we simulated 1bit fulladder to compare proposed logic with other logics to prove improved performance. As a result, proposed logic is improved NED and NSD to 60% and power consumption reduces about 55% than any other logics.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.3
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• pp.105-108
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• 2015

In this paper, we propose a differential fault analysis on symmetric SPN block cipher with bitslice involution S-box in 2011. The target block cipher was designed using AES block cipher and has advantage about restricted hardware and software environment using the same structure in encryption and decryption. Therefore, the target block cipher must be secure for the side-channel attacks. However, to recover the 128-bit secret key of the targer block cipher, this attack requires only one random byte fault and an exhausted search of $2^8$. This is the first known cryptanalytic result on the target block cipher.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.77-86
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• 2010

This paper presents an efficient secure scan design technique which is based on a fake key and IEEE 1149.1 instruction to protect secret key from scan-based side channel attack for an Advanced Encryption Standard (AES) core embedded on an System-on-a-Chip (SoC). Our proposed secure scan design technique can be applied to crypto IP core which is optimized for applications without the IP core modification. The IEEE 1149.1 standard is kept, and low area, low power consumption, very robust secret-key protection and high fault coverage can be achieved compared to the existing methods.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.6
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• pp.1117-1127
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• 2014

Differential Fault Analysis(DFA) is widely known for one of the most powerful method for analyzing block cipher. it is applicable to block cipher such as DES, AES, ARIA, SEED, and lightweight block cipher such as PRESENT, HIGHT. In this paper, we introduce a differential fault analysis on the lightweight block cipher LEA for the first time. we use 300 chosen fault injection ciphertexts to recover 128-bit master key. As a result of our attack, we found a full master key within an average of 40 minutes on a standard PC environment.

• The KIPS Transactions:PartC
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• v.18C no.4
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• pp.213-216
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• 2011

Differential Power Analysis is fully affected by various noises including temporal misalignment. Recently, Ryoo et al have introduced an efficient preprocessor method leading to improvements in DPA by removing the noise signals. This paper experimentally proves that the existing preprocessor method is not applied to all processor. To overcome this defect, we propose a Differential Trace Model(DTM). Also, we theoretically prove and experimentally confirm that the proposed DTM suites DPA.

• Proceedings of the Korea Information Processing Society Conference
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• 2024.05a
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• pp.367-370
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• 2024

양자컴퓨터 시대가 눈앞에 도래한 지금 차세대 암호로 주목받고 있는 양자 내성 암호는 다양한 수학적 알고리즘에 안전성을 기반하고 있으나 이 안전성을 위협하는 대표적인 공격 기법 중 하나인 부채널 분석 공격에 대응하기 위한 노력들이 계속되어 왔다. 이 논문에서는 코드 기반 양자 내성 암호를 중심으로 알고리즘에 위협적인 부채널 분석 공격에 대한 연구 동향을 분석하였다. 그리고 NIST 에서 PQC 표준화를 위해 Round 를 진행 중인 후보 중 하나인 코드 기반 알고리즘 MEDS 에 대해 소개하고, MEDS 알고리즘의 최적화를 위해 기존에 연구되었던 코드 기반 암호에 대한 부채널 분석 공격 대응 측면에서의 알고리즘의 안전성 확보라는 보안 비용과 하드웨어 가속 등을 통한 성능 향상이 적절한 조화를 이룰 수 있도록 설계하기 위한 방안에 대해 알아보았다.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.38 no.1
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• pp.43-57
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• 2002

This paper introduces an analysis method to predicting the flow characteristic of flow field around otter board In order to develope a high performance model. In this experiment, it is used a numerical analysis of flow field through CFD(Computational Fluid Dynamic), PIV method in which quantitative, qualitative evaluation is possible. In this experiment, it is used PIV method with flow filed image around otter board in order to analysis of flow characteristic. The result compared flow pattern with analysis result through CFD and also measurement result of lift and drag force coefficient carried out in CWC(Circulating Water Channel). The numerical analysis result is matched well with experiment result of PIV in the research and it is able to verify In the physical aspect. The result is as follows ; (1) It was carried out visibility experiment using laser light sheet, and picture analysis through PIV method in order to analysis fluid field of otter-board. As a result, the tendency of qualitative fluid movement only through the fluid particle's flow could be known. (2) Since PIV analysis result is quantitative, this can be seen in velocity vector distributions, instantaneous streamline contour, and average vorticity distributions through various post processing method. As a result, the change of flow field could be confirmed. (3) At angle of attack 24$^{\circ}$ where It Is shown maximum spreading force coefficient, the analysis result of CFD and PIV had very similar flow pattern. In both case, at the otter-board post edge a little boundary layer separation was seen, but, generally they had a good flow (4) As the result of post processing with velocity vector distributions, instantaneous streamline contour and average vorticity distributions by PIV, boundary layer separation phenomenon started to happen from angle of attack 24$^{\circ}$, and from over angle of attack 28$^{\circ}$, it happen at leading edge side with the width enlarged.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.1
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• pp.153-166
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• 2011

Recent trends in mobile device market whose services are rapidly expanding to provide wireless internet access are drawing people's attention to mobile security. Especially, since threats to information leakage are reaching to the critical level due to the frequent interchange of important data such as personal and financial information through wireless internet, various encryption algorithms has been developed to protect them. The encryption algorithms confront the serious threats by the appearance of side channel attack (SCA) which uses the physical leakage information such as timing, and power consumption, though the their robustness to threats is theoretically verified. Against the threats of SCA, researches including the performance and development direction of SCA should precede. Among tile SCA methods, the power analysis (PA) attack overcome this misalignment problem. The conventional methods require large computational power and they do not effectively deal with the delay changes in a power trace. To overcome the limitation of the conventional methods, we proposed a novel alignment method using peak matching. By computer simulations, we show the advantages of the proposed method compared to the conventional alignment methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.73-84
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• 2004

This paper suggests a new scalar multiplication algerian to resist SPA which threatens the security of cryptographic primitive on the hardware recently, and discusses how to apply this algerian Our algorithm is better than other SPA countermeasure algorithms aspect to computational efficiency. Since known SPA countermeasure algorithms have dependency of computation. these are difficult to construct parallel architecture efficiently. To solve this problem our algorithm removes dependency and computes a multiplication and a squaring during inversion with parallel architecture in order to minimize loss of performance. We implement hardware logic with VHDL(VHSIC Hardware Description Language) to verify performance. Synthesis tool is Synplify Pro 7.0 and target chip is Xillinx VirtexE XCV2000EFGl156. Total equivalent gate is 60,508 and maximum frequency is 30Mhz. Our scalar multiplier can be applied to digital signature, encryption and decryption, key exchange, etc. It is applied to a embedded-micom it protects SPA and provides efficient computation.