• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.97.1-97.1
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• 2010

유연금속기판위에 DC 마그네트론 스퍼터링을 이용하여 Ag/ZnO 이중구조의 후면반사막을 증착하고 Ag 표면조도 변화에 따른 후면반사막의 반사특성 변화와 플렉서블 비정질 실리콘 박막 태양전지의 셀 특성에 미치는 영향을 조사하였다. Substrate구조를 갖는 플렉서블 실리콘 박막 태양전지에서는 실리콘 박막 광흡수층의 상대적으로 낮은 광 흡수율로 인하여 입사광에 대한 태양전지 내에서의 광 산란 및 포획이 태양전지 효율을 증대시키는데 매우 중요한 역할을 하는 것으로 알려져 있다. 플렉서블 실리콘 박막 태양전지에서의 후면반사막은 광 흡수층에서 흡수되지 않는 입사광을 다시 반사시켜 광 흡수를 증대시키며 이때 후면반사막 표면에서 반사 빛을 효율적으로 산란시켜 이동경로를 증대시킴으로써 광 흡수율을 더욱 향상시킬 수 있다. 본 연구에서는 유연금속 기판위에 Ag와 ZnO:Al($Al_2O_3$ 2.5wt%) 타겟을 사용한 DC 마그네트론 스퍼터링법으로 Ag/AZO 이중구조의 후면반사막을 제조하고, Ag 박막의 표면형상 변화와 이에 따른 후면반사막의 반사도 변화를 비교, 분석하였다. 증착 조건 변화에 따른 표면 형상 및 반사 특성은 Atomic Force Mircroscope(AFM), Scanning electron miroscopy(SEM), UV-visible-nIR spectrometry를 통하여 분석하였다. 서로 다른 표면 거칠기를 갖는 후면반사막 위에 n-i-p구조의 a-Si:H 실리콘 박막 태양전지를 제조한 후 태양전지 동작 특성에 미치는 영향을 조사하였다. n,p층은 13.56MHz PECVD, i층은 60MHz VHF CVD를 사용하여 각각 제조 하였으며, Photo I-V, External Quantum Efficiency(EQE) 분석을 통하여 태양전지 특성을 조사 하였다. SEM 분석결과 공정 온도가 증가 할수록 Ag 박막의 표면 결정립 크기도 증가하였으며, AFM분석을 통한 Root-mean-square(Rms)값은 상온에서 $500^{\circ}C$로 증착온도가 증가함에 따라 6.62nm에서 46.64nm까지 증가하였다. Ag 박막의 표면 거칠기 증가에 따라 후면반 사막의 확산 반사도도 함께 증가하였다. 공정온도 $500^{\circ}C$에서 증착된 후면반사막을 사용하여 a-Si:H 태양전지를 제조하였을 때 상온에서 제조한 후면반사막에 비하여 단락전류밀도 (Jsc)값은 9.94mA/$cm^2$에서 13.36mA/$cm^2$로 증가하였으며, 7.6%의 가장 높은 태양전지 효율을 나타내었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.348-348
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• 2014

차세대 디스플레이 구동 회로 소자를 위한 재료로서, Amorphous Oxide Semiconductor (AOS)가 주목받고 있다. AOS는 기존의 Amorphous Silicon과 비교하여 뛰어난 이동도를 가지고 있으며, 넓은 밴드 갭에 의한 투명한 광학적 특성을 가지고 있다. 이러한 장점을 이용하여, AOS 박막은 thin film transistor (TFT)의 active channel로 이용 되고 있다. 하지만, AOS를 이용한 TFT의 경우, 시간이 경과함에 따라 $O_2$ 및 $H_2O$ 흡착에 의해 전기적 특성이 변하는 현상이 있다. 이러한 현상은 소자의 신뢰성에 있어 중요한 문제가 된다. 이러한 문제를 연구하기 위해 본 논문에서는, AOS 박막을 이용하여 bottom 게이트형 TFT를 제작하였다. 이를 위해 먼저, p-type Si 위에 건식산화방식으로 $SiO_2$(100 nm)를 성장시켜 게이트 산화막으로 이용하였다. 그리고 Zn과 Sn이 1: 2의 조성비를 가진 ZnSnO (ZTO) 용액을 제조한 후, 게이트 산화막 위에 spin coating 하였다. Splin coating된 용액에 남아 있는 솔벤트를 제거하기 위해 10분 동안 $230^{\circ}C$로 열처리를 한 후, 포토리소그래피와 에칭 공정을 이용하여 ZTO active channel을 형성하였다. 그 후, 박막 내에 남아 있는 불순물을 제거하고 ZTO TFT의 전기적인 특성을 향상시키기 위하여, $600^{\circ}C$의 열처리를 30분 동안 진행 하여 junctionless형 TFT 제작을 완료 하였다. 제작된 소자의 시간 경과에 따른 열화를 확인하기 위하여, 대기 중에서 2시간마다 HP-4156B 장비를 이용하여 전기적인 특성을 확인 하였으며, 이러한 열화는 후처리 공정을 통하여 회복시킬 수 있었다. 열화의 회복을 위한 후처리 공정으로, 퍼니스를 이용한 고온에서의 열처리와 microwave를 이용하여 저온 처리를 이용하였다. 결과적으로, TFT는 소자가 제작된 이후, 시간에 경과함에 따라서 on/off ratio가 감소하여 열화되는 경향을 보여 주었다. 이러한 현상은, TFT 소자의 ZTO back-channel에 대기 중에 있는 $O_2$ 및 $H_2O$의 분자의 물리적인 흡착으로 인한 것으로 보인다. 그리고 추가적인 후처리 공정들에 통해서, 다시 on/off ratio가 회복 되는 현상을 확인 하였다. 이러한 추가적인 후처리 공정은, 열화된 소자에 퍼니스에 의한 고온에서의 장시간 열처리, microwave를 이용한 저온에서 장시간 열처리, 그리고 microwave를 이용한 저온에서의 단 시간 처리를 수행 하였으며, 모든 소자에서 성공적으로 열화 되었던 전기적 특성이 회복됨을 확인 할 수 있었다. 이러한 결과는, 저온임에도 불구하고, microwave를 이용함으로 인하여, 물리적으로 흡착된 $O_2$ 및 $H_2O$가 짧은 시간 안에 ZTO TFT의 back-channel로부터 탈착이 가능함과 동시에 소자의 특성을 회복 가능 함 의미한다.

• Journal of the Korean institute of surface engineering
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• v.53 no.3
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• pp.124-129
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• 2020

This study is for the development of high temperature ALD SiO₂ film process, optimized for gap-fill process in manufacturing memory products, using a space-divided PE-ALD system equipped with an independent control dual plasma system and orbital moving unit. Space divided PE-ALD System has high productivity, and various applications can be applied according to Top Lid Design. But space divided ALD system has a limitation to realize concentric deposition map due to process influence due to disk rotation. In order to solve this problem, we developed an orbit rotation moving unit in which disk and wafer. Also we used Independent dual plasma system to enhance thin film properties. Improve productivity and film density for gap-fill process by having deposition and surface treatment in one cycle. Optimize deposition process for gap-fill patterns with different depths by utilizing our independently controlled dual plasma system to insert N₂and/or He plasma during surface treatment, Provide void-free gap-fill process for high aspect ratio gap-fill patterns (up to 50:1) with convex curvature by adjusting deposition and surface treatment recipe in a cycle.

• Journal of the Korean Society of Industry Convergence
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• v.23 no.1
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• pp.25-32
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• 2020

Generally, high-temperature, high-pressure, high-priced sintering equipment is used for diamond sintering, and conductivity is a problem for improving the surface modification of the sintered body. In this study, to improve the efficiency of diamond sintering, we identified a new process and material that can be sintered at low temperature, and attempted to develop a composite thin film that can be discharged by doping boron gas to improve the surface modification of the sintered body. Sintered bodies were sintered by mixing Si and two diamonds in different particle sizes based on CIP molding and HIP molding. In CVD deposition, CVD was performed using WC-Co cemented carbide using CH₄ and H₂ gas, and the specimen was made conductive using boron gas. According to the experimental results of the sintered body, as the Si content is increased, the Vickers hardness decreases drastically, and the values of tensile strength, Young's modulus and fracture toughness greatly increase. Conductive CVD deposited diamond was boron deposited and discharged. As the amount of boron added increased, the strength of diamond peaks decreased and crystallinity improved. In addition, considering the release processability, tool life and adhesion of the deposition surface according to the amount of boron added, the appropriate amount of boron can be confirmed. Therefore, by solving the method of low temperature sintering and conductivity problem, the possibility of solving the existing sintering and deposition problem is presented.

• Corrosion Science and Technology
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• v.9 no.2
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• pp.81-86
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• 2010

The mechanisms of selective oxidation of intercritically annealed CMnAl TRIP steels in a Continuous Galvanizing Line (GCL) were studied by cross-sectional observation of the surface and sub-surface regions by means of High Resolution Transmission Electron Microscopy (HR-TEM). The selective oxidation and nitriding of an intercritically annealed CMnAl TRIP steel in a controlled dew point 10%$H_2+N_2$ atmosphere resulted in the formation of c-xMnO.$MnO_2$ (1${\leq}$x<3) and c-xMnO.$Al_2O_3$ ($x{\geq}1$) particles on the steel surface. Single crystal c-xMnO.$SiO_2$ ($2{\leq}x{\leq}4$) oxide particles were also observed on the surface. A thin film of crystalline c-xMnO.$SiO_2$ (2${\leq}$x<3) and c-xMnO.$Al_2O_3$ ($x{\geq}1$) was present between these particles. In the sub-surface region, internal oxidation, nitriding and intermetallic compound formation were observed. In the first region, large crystalline c-xMnO.$SiO_2$ ($1{\geq}x{\geq}2$) and c-xMnO.$Al_2O_3$ ($x{\geq}1$) oxides particles were present. In the second region, c-AlN particles were observed, and in a third region, small $MnAl_x$ (x>1) intermetallic compound particles were observed.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.138-143
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• 2022

We analyzed the influence of post-annealing on Ga₂O₃/n-type 4H-SiC heterojunction diode. Gallium oxide (Ga₂O₃) thin films were deposited by radio frequency (RF) sputtering. Post-deposition annealing at 950℃ in an Oxygen atmosphere was performed. The material properties of Ga₂O₃ and the electrical properties of the diodes were investigated. Atomic Force Microscopy (AFM), X-Ray Diffraction and Scanning Electron Microscope (SEM) images show a significant increase in the roughness and crystallinity of the O₂-annealed films. After Oxygen annealing X-ray Photoelectron Spectroscopy (XPS) shows that the atomic ratio of oxygen increases which is related to a decrease in oxygen vacancy within the Ga₂O₃ film. The O₂-annealed diodes exhibited higher on-current and lower leakage current. Moreover, the ideality factor, barrier height, and thermal activation energy were derived from the current-voltage curve by increasing the temperature from 298 - 434K.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.3
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• pp.279-284
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• 2014

This paper proposes a novel OLED pixel circuit to compensate the threshold voltage variation of p-channel low temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The proposed 5-TFT OLED pixel circuit consists of 4 switching TFTs, 1 OLED driving TFT and 1 capacitor. One frame of the proposed pixel circuit is divided into initialization period, threshold voltage sensing and data programming period, data holding period and emission period. SmartSpice simulation results show that the maximum error rate of OLED current is -4.06% when the threshold voltage of driving TFT varies by ${\pm}0.25V$ and that of OLED current is 9.74% when the threshold voltage of driving TFT varies by ${\pm}0.50V$. Thus, the proposed 5T1C pixel circuit can realize uniform OLED current with high immunity to the threshold voltage variation of p-channel poly-Si TFT.

• Journal of the Korean Vacuum Society
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• v.16 no.5
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• pp.366-370
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• 2007

Nano-scopic holes which are distributed densely and uniformly were fabricated on $SiO_2$ surface. Self-assembling resists were used to produce a layer of uniformly distributed parallel poly methyl methacrylate (PMMA) cylinders in a polystyrene (PS) matrix. The PMMA cylinders were degraded and removed by acetic acid rinsing. Subsequently, PS nanotemplates were fabricated. The patterned holes of PS template were approximately $8{\sim}30\;nm$ wide, 40 nm deep, and 60 nm apart. The porous PS template was used as a dry etching mask to transfer the pattern of PS template into the silicon oxide thin film during reactive ion etching (RIE) process. The sizes of the patterned holes on $SiO_2$ layer were $9{\sim}33\;nm$. After pattern transfer by RIE, uniformly distributed holes of which size were in the range of $6{\sim}22\;nm$ were fabricated on Si substrate. Sizes of the patterned holes were controllable by PMMA molecular weight.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.168-168
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• 2008

Dimension of a transistor has rapidly shrunk to increase the speed of device and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate dioxide layer and low conductivity characteristic of poly-Si gate in nano-region. To cover these faults, study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$, and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-Si gate is not compatible with high-k materials for gate-insulator. Poly Si gate with high-k material has some problems such as gate depletion and dopant penetration problems. Therefore, new gate structure or materials that are compatible with high-k materials are also needed. TiN for metal/high-k gate stack is conductive enough to allow a good electrical connection and compatible with high-k materials. According to this trend, the study on dry etching of TiN for metal/high-k gate stack is needed. In this study, the investigations of the TiN etching characteristics were carried out using the inductively coupled $BCl_3$-based plasma system and adding $Cl_2$ gas. Dry etching of the TiN was studied by varying the etching parameters including $BCl_3$/Ar gas mixing ratio, RF power, DC-bias voltage to substrate, and $Cl_2$ gas addition. The plasmas were characterized by optical emission spectroscopy analysis. Scanning electron microscopy was used to investigate the etching profile.

• Journal of Sensor Science and Technology
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• v.29 no.5
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• pp.354-359
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• 2020

The high vacuum hermetic sealing technique ensures excellent performance of MEMS resonators. For the high vacuum hermetic sealing, the customization of anodic bonding equipment was conducted for the glass/Si/glass triple-stack anodic bonding process. Figure 1 presents the schematic of the MEMS resonator with triple-stack high-vacuum anodic bonding. The anodic bonding process for vacuum sealing was performed with the chamber pressure lower than 5 × 10^-6 mbar, the piston pressure of 5 kN, and the applied voltage was 1 kV. The process temperature during anodic bonding was 400 ℃. To maintain the vacuum condition of the glass cavity, a getter material, such as a titanium thin film, was deposited. The getter materials was active at the 400 ℃ during the anodic bonding process. To read out the electrical signals from the Si resonator, a vertical feed-through was applied by using through glass via (TGV) which is formed by sandblasting technique of cap glass wafer. The aluminum electrodes was conformally deposited on the via-hole structure of cap glass. The TGV process provides reliable electrical interconnection between Si resonator and aluminum electrodes on the cap glass without leakage or electrical disconnection through the TGV. The fabricated MEMS resonator with proposed vacuum packaging using three-layer anodic bonding process has resonance frequency and quality factor of about 16 kHz and more than 40,000, respectively.