• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.159-167
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• 2005

Quantization effects (QEs), which manifests when the device dimensions are comparable to the de Brogile wavelength, are becoming common physical phenomena in the present micro-/nanometer technology era. While most novel devices take advantage of QEs to achieve fast switching speed, miniature size and extremely small power consumption, the mainstream CMOS devices (with the exception of EEPROMs) are generally suffering in performance from these effects. In this paper, an analytical model accounting for the QEs and poly-depletion effects (PDEs) at the silicon (Si)/dielectric interface describing the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of MOS devices with thin oxides is developed. It is also applicable to multi-layer gate-stack structures, since a general procedure is used for calculating the quantum inversion charge density. Using this inversion charge density, device characteristics are obtained. Also solutions for C-V can be quickly obtained without computational burden of solving over a physical grid. We conclude with comparison of the results obtained with our model and those obtained by self-consistent solution of the $Schr{\ddot{o}}dinger$ and Poisson equations and simulations reported previously in the literature. A good agreement was observed between them.

• Journal of IKEEE
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• v.14 no.4
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• pp.277-282
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• 2010

In this paper, we proposed ZnO trench Static Induction Transistor(SIT). Because The compound semiconductor had superior thermal characteristics, ZnO and SiC power devices is next generation power semiconductor devices. We carried out modeling of ZnO SIT with 2-D device and process simulator. As a result of modeling, we obtained 340V breakdown voltage. The channel thickness was 3um and the channel doping concentration is 1e17cm-3. And we carried out thermal characteristics, too.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.211-212
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• 2010

GaN 기반의 상부발광형 LED는 동작되는 동안 생기는 전기적 단락, 그리고 칩 위의 p-형 전극과 n-형 전극 사이에 생기는 누설전류 및 신뢰성 확보를 위하여 칩 표면에 passivation 층을 형성하게 된다. SiO2, Si3N4와 같은 passivation layers는 일반적으로 PECVD (Plasma Enhanced Chemical Vapor Deposition)공정을 이용한다, 하지만 이는 공정 특성상 plasma로 인한 damage가 유발되기 때문에 표면 누설 전류가 증가 한다. 이로 인해 forward voltage와 reverse leakage current의 특성이 저하된다. 본 실험에서는 원자층 단위의 박막 증착으로 인해 PECVD보다 단차 피복성이 매우 우수한 PEALD(Plasma Enhanced Atomic Layer Deposition)공정을 이용하여 Al2O3 passivation layer를 증착한 후, 표면 누설전류와 빛의 출력 특성에 대해서 조사해 보았다. PSS (patterned sapphire substrate) 위에 성장된 LED 에피구조를 사용하였고, TCP(Trancformer Copled Plasma)장비를 사용하여 에칭 공정을 진행하였다. 이때 투명전극을 증착하기 위해 e-beam evaporator를 사용하여 Ni/Au를 각각 $50\;{\AA}$씩 증착한 후 오믹 특성을 향상시키기 위하여 $500^{\circ}C$에서 열처리를 해주었다. 그리고 Ti/Au($300/4000{\AA}$) 메탈을 사용하여 p-전극과 n-전극을 형성하였다. Passivation을 하지 않은 경우에는 reverse leakage current가 -5V 에서 $-1.9{\times}10-8$ A 로 측정되었고, SiO2와 Si3N4을 passivation으로 이용한 경우에는 각각 $8.7{\times}10-9$과 $-2.2{\times}10-9$로 측정되었다. Fig. 1 에서 보면 알 수 있듯이 5 nm의 Al2O3 film을 passivation layer로 이용할 경우 passivation을 하지 않은 경우를 제외한 다른 passivation 경우보다 reverse leakage current가 약 2 order ($-3.46{\times}10-11$ A) 정도 낮게 측정되었다. 그 이유는 CVD 공정보다 짧은 ALD의 공정시간과 더 낮은 RF Power로 인해 plasma damage를 덜 입게 되어 나타난 것으로 생각된다. Fig. 2 에서는 Al2O3로 passivation을 한 소자의 forward voltage가 SiO2와 Si3N4로 passivation을 한 소자보다 각각 0.07 V와 0.25 V씩 낮아지는 것을 확인할 수 있었다. 또한 Fig. 3 에서는 Al2O3로 passivation을 한 소자의 output power가 SiO2와 Si3N4로 passivation을 한 소자보다 각각 2.7%와 24.6%씩 증가한 것을 볼 수 있다. Output power가 증가된 원인으로는 향상된 forward voltage 및 reverse에서의 leakage 특성과 공기보다 높은 Al2O3의 굴절률이 광출력 효율을 증가시켰기 때문인 것으로 판단된다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.71-71
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• 2012

As the critical dimensions of integrated circuits are scaled down, the line width and spacing between the metal interconnects are made smaller. The dielectric film used as insulation between the metal lines contributes to the resistance-capacitance (RC) time constant that governs the device speed. If the RC time delay, cross talk and lowering the power dissipation are to be reduced, the intermetal dielectric (IMD) films should have a low dielectric constant. The introduction of Cu and low-k dielectrics has incrementally improved the situation as compared to the conventional $Al/SiO_2$ technology by reducing both the resistivity and the capacitance between interconnects. Some of the potential candidate materials to be used as an ILD are organic and inorganic precursors such as hydrogensilsequioxane (HSQ), silsesquioxane (SSQ), methylsilsisequioxane (MSQ) and carbon doped silicon oxide (SiOCH), It has been shown that organic functional groups can dramatically decrease dielectric constant by increasing the free volume of films. Recently, various inorganic precursors have been used to prepare the SiOCH films. The k value of the material depends on the number of $CH_3$ groups built into the structure since they lower both polarity and density of the material by steric hindrance, which the replacement of Si-O bonds with Si-$CH_3$ (methyl group) bonds causes bulk porosity due to the formation of nano-sized voids within the silicon oxide matrix. In this talk, we will be introduce some properties of SiOC(-H) thin films deposited with the dimethyldimethoxysilane (DMDMS: $C_4H_{12}O_2Si$) and oxygen as precursors by using plasma-enhanced chemical vapor deposition with and without ultraviolet (UV) irradiation.

• Korean Journal of Metals and Materials
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• v.50 no.4
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• pp.331-337
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• 2012

Electrical properties as a function of composition in silicon nitride ($SiN_x$) films grown at low temperatures ($<200^{\circ}C$) were studied for applications to photonic devices and thin film transistors. Both silicon-rich and nitrogen-rich compositions were successfully produced in final films by controlling the source gas mixing ratio, $R=[(N_2\;or\;NH_3)/SiH_4]$, and the RF plasma power. Depending on the film composition, the dielectric and optical properties of $SiN_x$ films varied substantially. Both the resistivity and breakdown field strength showed the maximum value at the stoichiometric composition (N/Si = 1.33), and degraded as the composition deviated to either side. The electrical properties degraded more rapidly when the composition shifted toward the silicon-rich side than toward the nitrogen-rich side. The composition shift from the silicon-rich side to the nitrogen-rich side accompanied the shift in the photoluminescence characteristic peak to a shorter wavelength, indicating an increase in the band gap. As long as the film composition is close to the stoichiometry, the breakdown field strength and the bulk resistivity showed adequate values for use as a gate dielectric layer down to $150^{\circ}C$ of the process temperature.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.12
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• pp.654-664
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• 2000

Thin films of ZnO are deposited by using an RF magnetron sputtering with varying the substrate temperature(RT~39$0^{\circ}C$) and RF power(50~250W). Cu-doped ZnO(denoted by ZnO:Cu) films have also been prepared by co-spputtering of a ZnO target on which some Cu-chips are attached. Different substrate materials, such as Si, $SiO_{2}/Si$, sapphire, DLC/Si, and poly-diamond/Si, are employed to compare the c-axial growth features of deposited ZnO films. Texture coefficient(TC) values for the (002)-preferential growth are estimated from the XRD spectra of deposited films. Optimal ranges of RF powers and substrate temperatures for obtaining high TC values are determined. Effects of Cu-doping conditions, such as relative Cu-chip sputtering areas, $O_{2}/(Ar+O_{2})$ mixing ratios, and reactor pressures, on TC values, electrical resistivities, and relative Cu-compositions of deposited ZnO:Cu films have been systematically investigated. XPS study shows that the relative densities of metallic $Cu(Cu^{0})$ atoms and $CuO(Cu^{2+})$-phases within deposited films may play an important role of determining their electrical resistivities. It should be noted from the experimental results that highly resistive(> $10^{10}{\Omega}cm$ ZnO films with high TC values(> 80%) can be achieved by Cu-doping. SAW devices with ZnO(or Zn):Cu)/IDT/$SiO_{2}$/Si configuration are also fabricated to estimate the effective electric-mechanical coupling coefficient($k_{eff}^{2}$) and the insertion loss. It is observed that the devices using the Cu-doped ZnO films have a higher $k_{eff}^{2}$ and a lower insertion loss, compared with those using the undoped films.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.34 no.1
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• pp.36-39
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• 2024

As interest in power semiconductors is growing recently, research on device design and application using light energy gap materials such as SiC and GaN is being actively conducted. Because AlN single crystals have a larger energy gap than the above mentioned materials, research on high-power devices is also in progress, but commercialized wafers have not yet been reported, so research is needed. In this study, we applied the HVPE (Hydride vapor phase epitaxy) method to produce AlN single crystals and attempted to obtain bulk single crystals using our own manufacturing equipment. To this end, we would like to report the results of securing the growth conditions for single crystals. we would like to report on the change in the shape of the grown crystal according to the change in temperature.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1359-1360
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• 2006

lTO(Indium-Tin-Oxide) was used as anode material for OLED. Characteristics of ITO have great effect on efficiency of OLEDS(Organic light emitting diodes). ITO surface was treated by Nd:YAG laser in order to improve its chemical properties, wettability, adhesive property and to remove the surface contaminants while maintaining its original function. In this study, main purpose was to improve the efficiency of OLEDs by the ITO surface treatment: ITO surface was treated using a Nd:YAG(${\lambda}=266nm$, pulse) with a fixed power of 0.06[w] and various stage scanning velocities. Surface morphology of the ITO was investigated by AFM. Test OLEDs with surface treated ITO were fabricated by deposition of TPD (HTL), Ald3 (ETL/TML) and Al (cathode) thin films. Device performance of the OLEDs such as V-I-L was investigated using Source Measurement Unit (SMU: Keithly. Model 2400) and Luminance Measurement (TOPCON. BM-8).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.2
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• pp.159-163
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• 2005

This paper gives characterization of ZnO thin film deposited by RF magnetron sputtering method, which is concerned in deposition process and device fabrication process, to fabricate solidly mounted resonator(SMR)-type film bulk acoustic resonator(FBAR). A piezoelectric layer of 1.1${\mu}{\textrm}{m}$ thick ZnO thin films were grown on thermally oxidized SiO$_2$(3000 $\AA$)/Si substrate layers by RF magnetron sputtering at the room temperature. The highly c-axis oriented ZnO thin film was obtained at the conditions of 265 W of RF power, 10 mtorr of working pressure, and 50/50 of Ar/O$_2$ gas ratio. The piezoelectric-active area was 50 ${\mu}{\textrm}{m}$${\times}$50${\mu}{\textrm}{m}$, and the thickness of ZnO film and Al-3 % Cu electrode were 1.4 ${\mu}{\textrm}{m}$ and 180${\mu}{\textrm}{m}$, respectively. Its series and parallel frequencies appeared at 2.128 and 2.151 GHz, respectively, and the qualify factor of the resonator was as high as 401.8$\pm$8.5.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.291-291
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• 2010

Electron-beam lithography (EBL) process is a versatile tool for a fabrication of nanostructures, nano-gap electrodes or molecular arrays and its application to nano-device. However, it is not appropriate for the fabrication of sub-5 nm features and high-aspect-ratio nanostructures due to the limitation of EBL resolution. In this study, the precision assembly and alignment of DNA molecule was demonstrated using sub-5 nm nanostructures formed by a combination of conventional electron-beam lithography (EBL) and plasma ashing processes. The ma-N2401 (EBL-negative tone resist) nanostructures were patterned by EBL process at a dose of $200\;{\mu}C/cm2$ with 25 kV and then were ashed by a chemical dry etcher at microwave (${\mu}W$) power of 50 W. We confirmed that this method was useful for sub-5 nm patterning of high-aspect-ratio nanostructures. In addition, we also utilized the surface-patterning technique to create the molecular pattern comprised 3-(aminopropyl) triethoxysilane (APS) as adhesion layer and octadecyltrichlorosilane (OTS) as passivation layer. DNA-templated gold nanoparticle chain was attached only on the sub-5 nm APS region defined by the amine groups, but not on surface of the OTS region. We were able to obtain DNA molecules aligned selectively on a SiO2/Si substrate using atomic force microscopy (AFM).