• Korean Journal of Materials Research
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• v.8 no.3
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• pp.229-237
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• 1998

We grew the hexagonal GaN films on (100) Si and (00.1) sapphire substrates in the temperature range of $300~730^{\circ}C$ by the direct reaction between thermally ionized N-source and thermally evaporated Ga-source. The GaN growth rates are increased at the initial stage of GaN formation and it was saturated to some values by the coalescence of each crystallites. The oxygen signal was observed in XPS spectra for all the GaN films grown in this work, especially low- temperature grown GaN film may due to incorporation of the residual oxygen in the growth chamber. The surface of low-temperature and shorter time grown films covered only Ga-droplets. however, with increasing the both substrate temperature and the growth time GaN is growth to crystallites. and coalescence to ring-type crystallites. With sufficient supply of N-source, they were changed to platelets. In the PL spectrum measured at 20 K, we observed the impurity related emission at 3.32eV and 3.38eV.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.254-254
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• 2011

The memories with nano-particles are very attractive because they are promising candidates for low operating voltage, long retention time and fast program/erase speed. In recent, various nano-floating gate memories with metal-oxide nanocrystals embedded in organic and inorganic layers have been reported. Because of the carrier generation in semiconductor, induced photon pulse enhanced the program/erase speed of memory device. We studied photo-induced electrical properties of these metal-oxide nanocrystal memory devices. At first, 2~10-nm-thick Sn and In metals were deposited by using thermal evaporation onto Si wafer including a channel with $n^+$ poly-Si source/drain in which the length and width are 10 ${\mu}m$ each. Then, a poly-amic-acid (PAA) was spin coated on the deposited Sn film. The PAA precursor used in this study was prepared by dissolving biphenyl-tetracarboxylic dianhydride-phenylene diamine (BPDA-PDA) commercial polyamic acid in N-methyl-2-pyrrolidon (NMP). Then the samples were cured at 400$^{\circ}C$ for 1 hour in N atmosphere after drying at 135$^{\circ}C$ for 30 min through rapid thermal annealing. The deposition of aluminum layer with thickness of 200 nm was followed by using a thermal evaporator, and then the gate electrode was defined by photolithography and etching. The electrical properties were measured at room temperature using an HP4156a precision semiconductor parameter analyzer and an Agilent 81101A pulse generator. Also, the optical pulse for the study on photo-induced electrical properties was applied by Xeon lamp light source and a monochromator system.

• Journal of the Korean Ceramic Society
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• v.41 no.1
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• pp.13-18
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• 2004

$La_{0.5}Sr_{0.5}CoO_3$ (LSCO) electrodes were prepared on ferroelectric $Sr_{0.9}Bi_{2.1}Ta_2O_9$(SBT) thin films by spin coating method using photosensitive sol-gel solution. Self-patterning technique of photosensitive sol-gel solution has advantages such as simple manufacturing process compared to photoresist/dry etching process. Lanthanum(III) 2-methoxyethoxide, Stronitium diethoxide. Cobalu(II)2-methoxyethoxide were used as starting materials for LSCO electrode. UV irradiation on LSCO thin films lead to decrease solubility by M-O-M bond formation and the solubility difference allows us to obtain self-patternine. There was little composition change of the LSCO thin films between before leaching and after leaching in 2-methoxyethanol. The lowest resistivity of LSCO thin films deposited on $SiO_2$/Si substrate was $1.1{\times}10^{-2}{\Omega}cm$ when the thin film was ennealed at $740^{\circ}C$. The values of Pr/Ps and 2Pr of LSCO/SBT/Pt capacitor on the applied voltage of 5V were 0.51, 8.89 ${\mu}C/cm^2$, respectively.

• Transactions on Electrical and Electronic Materials
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• v.5 no.5
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• pp.169-172
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• 2004

Deep sub-micron device required to get the superior ultra thin gate oxide characteristics. In this research, I will recommend a novel shallow trench isolation structure(STI) for thin gate oxide and a $N_2$O gate oxide 30 $\AA$ by NO ambient process. The local oxidation of silicon(LOCOS) isolation has been replaced by the shallow trench isolation which has less encroachment into the active device area. Also for $N_2$O gate oxide 30 $\AA$, ultra thin gate oxide 30 $\AA$ was formed by using the $N_2$O gate oxide formation method on STI structure and LOCOS structure. For the metal electrode and junction, TiSi$_2$ process was performed by RTP annealing at 850 $^{\circ}C$ for 29 sec. In the viewpoints of the physical characteristics of MOS capacitor, STI structure was confirmed by SEM. STI structure was expected to minimize the oxide loss at the channel edge. Also, STI structure is considered to decrease the threshold voltage, result in a lower Ti/TiN resistance( Ω /cont.) and higher capacitance-gate voltage(C- V) that made the STI structure more effective. In terms of the TDDB(sec) characteristics, the STI structure showed the stable value of 25 % ～ 90 % more than 55 sec. In brief, analysis of the ultra thin gate oxide 30 $\AA$ proved that STI isolation structure and salicidation process presented in this study. I could achieve improved electrical characteristics and reliability for deep submicron devices with 30 $\AA$ $N_2$O gate oxide.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.396-396
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• 2013

The resistive random access memory (ReRAM) has several advantages to apply next generation non-volatile memory device, because of fast switching time, long retentions, and large memory windows. The high mobility of monolayered graphene showed several possibilities for scale down and electrical property enhancement of memory device. In this study, the monolayered graphene grown by chemical vapor deposition was transferred to $SiO_2$ (100 nm)/Si substrate and glass by using PMMA coating method. For formation of metal-oxide nanoparticles, we used a chemical reaction between metal films and polyamic acid layer. The 50-nm thick BPDA-PDA polyamic acid layer was coated on the graphene layer. Through soft baking at $125^{\circ}C$ or 30 min, solvent in polyimide layer was removed. Then, 5-nm-thick indium layer was deposited by using thermal evaporator at room temperature. And then, the second polyimide layer was coated on the indium thin film. After remove solvent and open bottom graphene layer, the samples were annealed at $400^{\circ}C$ or 1 hr by using furnace in $N_2$ ambient. The average diameter and density of nanoparticle were depending on annealing temperature and times. During annealing process, the metal and oxygen ions combined to create $In_2O_3$ nanoparticle in the polyimide layer. The electrical properties of $In_2O_3$ nanoparticle ReRAM such as current-voltage curve, operation speed and retention discussed for applictions of transparent and flexible hybrid ReRAM device.

• ETRI Journal
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• v.16 no.1
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• pp.45-57
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• 1994

The effects of reactive ion etching (RIE) of $SiO_2$ layer in $CHF_3/C_2F_6$ on the underlying Si surface have been studied by X-ray photoelectron spectroscopy (XPS), secondary ion mass spectrometer, Rutherford backscattering spectroscopy, and high resolution transmission electron microscopy. We found that two distinguishable modified layers are formed by RIE : (i) a uniform residue surface layer of 4 nm thickness composed entirely of carbon, fluorine, oxygen, and hydrogen with 9 different kinds of chemical bonds and (ii) a contaminated silicon layer of about 50 nm thickness with carbon and fluorine atoms without any observable crystalline defects. To search the removal condition of the silicon surface residue, we monitored the changes of surface compositions for the etched silicon after various post treatments as rapid thermal anneal, $O_2$, $NF_3$, $SF_6$, and $Cl_2$ plasma treatments. XPS analysis revealed that $NF_3$ treatment is most effective. With 10 seconds exposure to $NF_3$ plasma, the fluorocarbon residue film decomposes. The remained fluorine completely disappears after the following wet cleaning.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.393-396
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• 2004

본 논문에서는 완충층용 MgO 박막을 P-type(100)Si 기판위에 작업가스 $Ar:O_2=80:20$, RF 파워 50W, 기판온도 $400^{\circ}C$, 10mtorr의 작업진공에서 $500{\AA}$ 증착하였다. 제작된 MgO/Si 기판위에 RF Magnetron sputtering법으로 작업가스 $Ar:O_2$의 비율을 90:10, 80:20, 70:30으로 변화하면서 $BST(Ba_{0.5}Sr_{0.5}TiO_3)$ 박막을 약 $2000{\AA}$ 증착하였다. XRD 측정결과 작업가스비의 변화에 관계없이(110)BST와 (111)BST 피크만이 관찰되었으며 작업가스 $Ar:O_2=80:20$에서 가장 양호한 결정성을 나타내었다. I-V 측정결과 인가전계 ${\pm}100kV/cm$에서 $10^{-7}A/cm^2$이하의 양호한 누설전류 특성을 보여주고 있으며 C-V 측정결과 작업가스 $Ar:O_2$의 비율 90:10, 80:20, 70:30에서의 비유전율은 각각 283, 305, 296으로서 작업가스비 80:20에서 제작된 박막의 특성이 가장 우수하였다. 작업가스비 80:20에서 제작된 박막의 SEM 측정결과 결정이 성장되었음을 확인할 수 있었고 그레인의 크기는 약 10nm였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.34 no.4
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• pp.251-255
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• 2021

a-Si is commonly considered as a primary candidate for the formation of passivation layer in heterojunction (HIT) solar cells. However, there are some problems when using this material such as significant losses due to recombination and parasitic absorption. To reduce these problems, a wide bandgap material is needed. A wide bandgap has a positive influence on effective transmittance, reduction of the parasitic absorption, and prevention of unnecessary epitaxial growth. In this paper, the adoption of a-SiO_x:H as the intrinsic layer was discussed. To increase lifetime and conductivity, oxygen concentration control is crucial because it is correlated with the thickness, bonding defect, interface density (D_it), and band offset. A thick oxygen-rich layer causes the lifetime and the implied open-circuit voltage to drop. Furthermore the thicker the layer gets, the more free hydrogen atoms are etched in thin films, which worsens the passivation quality and the efficiency of solar cells. Previous studies revealed that the lifetime and the implied voltage decreased when the a-SiOx thickness went beyond around 9 nm. In addition to this, oxygen acted as a defect in the intrinsic layer. The D_it increased up to an oxygen rate on the order of 8%. Beyond 8%, the D_it was constant. By controlling the oxygen concentration properly and achieving a thin layer, high-efficiency HIT solar cells can be fabricated.

• Bulletin of the Korean Chemical Society
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• v.31 no.9
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• pp.2503-2508
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• 2010

ZnO thin films were grown on Si or $SiO_2$/Si substrates, at growth temperatures ranging from 150 to $400^{\circ}C$, by atomic layer deposition (ALD) using diethylzinc and water. Despite the large band gap of 3.3 eV, the ALD ZnO films show high n-type conductivity, i.e. low resistivity in the order of $10^{-3}\;{\Omega}cm$. In order to understand the high conductivity of ALD ZnO films, the films were characterized with X-ray diffraction, transmission electron microscopy, X-ray photoelectron spectroscopy, elastic recoil detection, Rutherford backscattering, Photoluminescence, and Raman spectroscopy. In addition, the various analytical data of the ZnO films were compared with those of ZnO single crystal. According to our analytical data, metallic zinc plays an important role for the high conductivity in ALD ZnO films. Therefore when the metallic zinc was additionally oxidized with ozone by a modified ALD sequence, the resistivity of ZnO films could be adjusted in a range of $3.8{\times}10^{-3}\;{\sim}\;19.0\;{\Omega}cm$ depending on the exposure time of ozone.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.71-71
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• 1999

현재 소자 제작에 응용되는 수소화된 비정질 실리콘은 PECVD 방법으로 제작하는 것이 보편적인 방법이다. 그러나 비정질 실리콘 박막 트랜지스터는 band gap edge 근처에서 국재준위가 많아 mobility가 작으며 상온에서 조차 불안정하여 신뢰성이 높지 않고, 도핑된 비정질 실리콘의 높은 비저항 등의 단점으로 인하여 고속 회로에 응용이 불가능하다. 반면 다결정질 실리콘 박막 트랜지스터는 a-Si:H TFT 에 비해 재현성이 우수하고 high resolution, high resolution, high contrast LCD에 응용할 수 있다. 하지만, 다결정 실리콘의 grain boundary로 인해 단결정에 비해 많은 defect 들이 존재하여 전도성을 감소시킨다. 따라서 Mobility를 증가시키기 위해서 grain size를 증가시키고 grain boundary 내에 존재하는 trap center를 감소시켜야 한다. 따라서 본 실험에서는 PECVD 장비로 초기 기판을 plasma 처리하여 다결정 실리콘 박막을 제작하여, 기판 처리에 대한 다결정 실리콘 박막의 성장의 특성을 조사하였다. 실험 방법으로는 PECVD 시스템을 이용하여 SiH4 gas와 H2 gas를 선택적으로 증착시키는 LBL 방법을 사용하여 $\mu$c-Si:H 박막을 제작하였다. 비정질 층을 gas plasma treatment 하여 다결정질 실리콘의 증착 initial stage 관찰을 주목적으로 관찰하였다. 다결정 실리콘 박막의 구조적 성질을 조사하기 위하여 Raman, AFM, SEM, XRD를 이용하여 grain 크기와 결정화도에 대해 측정하여 결정성장 mechanism을 관측하였다. LBL 방법으로 증착시킨 박막의 Raman 분석을 통해서 박막 증착 초기에 비정질이 증착된 후에 결정질로 상태가 변화됨을 관측할 수 있었고, SEM image를 통해서 증착 회수를 증가시키면서 grain size가 작아졌다 다시 커지는 현상을 볼 수 있었다. 이 비정질 층의 transition layer를 gas plasma 처리를 통해서 다결정 핵 형성에 영향을 관측하여 적정한 gas plasma를 통해서 다결정질 실리콘 박막 증착 공정을 단축시킬 수 있는 가능성을 짐작할 수 있었고, 또한 표면의 roughnes와 morphology를 AFM을 통하여 관측함으로써 다결정 박막의 핵 형성에 알맞은 증착 표면 특성을 분석 할 수 있었다.