• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.13-16
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• 2001

반도체 동작시에 파워 손실을 최소화하는 것은 2000년대의 에너지, 산업전자, 정보통신 산업분야에서의 가장 주요한 요구 사항중의 하나이다. 실리콘계 반도체 소자들은 완전히 새로운 구동기구의 소자가 개발되지 않는 한, 실리콘 재료의 낮은 열 전도율이나 낮은 절연파괴전계와 같은 물리적 특성한계 때문에 이러한 요구를 만족시키는 것이 불가능한 실정이다. 따라서 21세기를 위한 대안으로 고열전도율의 WBG(Wide Band-Gap) 물질 그 중에서도 탄화규소(SiC) 반도체가 제시되고 있다. SiC 반도체는 실리콘에 비하여 밴드 갭(band gap: E$_{g}$)이 높을 뿐만이 아니라 절연파괴강도(E$_{B}$)가 한 자릿수 이상 그리고 전자의 포화 drift 속도, v$_{s}$ 및 열전도도 k가 3배 가량 크다. 따라서 SiC는 고온 동작 내지는 고내압, 대전류, 저손실 반도체를 제작하는데 아주 유리하다. 본고에서는 응용성이 넓고, 단결정 제조가 비교적 용이한 SiC 반도체의 기술현황 에 대하여 살펴보고자 한다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.238-242
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• 2001

In this paper, the current-voltage characteristics of a 4H-SiC MESFET is simulated by using the Atlas Simulation tool. we are able to use the simulator to extract more information about the new material 4H-SiC, including the mobility, velocity-field Curve and the Schottky barrier height. We have enabled and used the new simulator to investigate breakdown Voltage and thus predict operation limitations of 4H-SiC device. Modeling results indicate that the Breakdown Voltage is 197 V and Current is 100 mA

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.188-189
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• 2017

There has been a growing demand for power semiconductor switches equipped with high-voltage blocking capability of kV range and fast-switching characteristics of ns range in various plasma application. This paper investigates the application of SiC MOSFETs in the particular plasma application which requires the blocking voltage of 4.5kV and the switching transient time of less than 100ns. In order to meet the required blocking voltage, the series connection of multiple SiC MOSFETs is adopted in this paper. Also, snubber capacitors are employed to equalize the voltage sharing among the series connected SiC MOSFETs. The simulation and experimental result successfully verifies the application of SiC MOSFETs and snubber capacitors in the plasma application requiring high-voltage and fast-switching load dynamics.

• Proceedings of the Materials Research Society of Korea Conference
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• 2002.05a
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• pp.124-124
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• 2002

• Journal of the Semiconductor & Display Technology
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• v.15 no.1
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• pp.52-55
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• 2016

GZO film was prepared on p-type Si wafer and then annealed at various temperatures in an air conditions to research the bonding structures in accordance with the annealing processes. GZO film annealed in an atmosphere showed the various bonding structure depending on annealing temperatures and oxygen gas flow rate during the deposition. The difference of bonding structures of GZO films made by oxygen gas flows between 18 sccm and 22 sccm was so great. The bonding structures of GZO films made by oxygen gas flow of 18 sccm were showed the crystal structure, but that of 22 sccm were showed the amorphous structure in spite of after annealing processes. The bonding structure of GZO as oxide-semiconductor was observed the trend of becoming amorphous structures at the temperature of $200^{\circ}C$. Therefore, the characteristics of oxide semiconductor are needed to research the variation near the annealing at $200^{\circ}C$.

• Journal of the Semiconductor & Display Technology
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• v.14 no.4
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• pp.45-49
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• 2015

Using a combined CVD and ALD equipment system, multi-layer quantum well structures of $Al_2O_3/a-Si/Al_2O_3$ were fabricated on silicon Schottky junction devices and implemented to quantum well solar cells, in which the 1~1.5 nm thicknesses of the aluminum oxide films and the a-Si thin film layers were deposited at $300^{\circ}C$ and $450^{\circ}C$, respectively. Fabricated solar cell was operated by tunneling phenomena through the inserted quantum well structure being generated electrons on the silicon surface. Efficiency of the fabricated solar cell inserted with multi-quantum well of 41 layers has been increased by about 10 times that of the solar cell of pure Schottky junction solar cell.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.9-15
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• 2018

This paper shows the principles and characteristics of the transient liquid phase (TLP) bonding technology for power modules packaging. The power module is semiconductor parts that change and manage power entering electronic devices, and demand is increasing due to the advent of the fourth industrial revolution. Higher operation temperatures and increasing current density are important for the performance of power modules. Conventional power modules using Si chip have reached the limit of theoretical performance development. In addition, their efficiency is reduced at high temperature because of the low properties of Si. Therefore, Si is changed to silicon carbide (SiC) and gallium nitride (GaN). Various methods of bonding have been studied, like Ag sintering and Sn-Au solder, to keep up with the development of chips, one of which is TLP bonding. TLP bonding has the advantages in price and junction temperature over other technologies. In this paper, TLP bonding using various materials and methods is introduced. In addition, new TLP technologies that are combined with other technologies such as metal powder mixing and ultrasonic technology are also reviewed.

• Transactions on Electrical and Electronic Materials
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• v.18 no.1
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• pp.55-57
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• 2017

Amorphous oxide thin film transistors (TFTs) were fabricated with 0.5 wt% silicon doped zinc tin oxide (a-0.5SZTO) thin film deposited by radio frequency (RF) magnetron sputtering. In order to investigate the effect of annealing treatment on the electrical properties of TFTs, a-0.5SZTO thin films were annealed at three different temperatures ($300^{\circ}C$, $500^{\circ}C$, and $700^{\circ}C$ for 2 hours in a air atmosphere. The structural and electrical properties of a-0.5SZTO TFTs were measured using X-ray diffraction and a semiconductor analyzer. As annealing temperature increased from $300^{\circ}C$ to $500^{\circ}C$, no peak was observed. This provided crystalline properties indicating that the amorphous phase was observed up to $500^{\circ}C$. The electrical properties of a-0.5SZTO TFTs, such as the field effect mobility (${\mu}_{FE}$) of $24.31cm^2/Vs$, on current ($I_{ON}$) of $2.38{\times}10^{-4}A$, and subthreshold swing (S.S) of 0.59 V/decade improved with the thermal annealing treatment. This improvement was mainly due to the increased carrier concentration and decreased structural defects by rearranged atoms. However, when a-0.5SZTO TFTs were annealed at $700^{\circ}C$, a crystalline peak was observed. As a result, electrical properties degraded. ${\mu}_{FE}$ was $0.06cm^2/Vs$, $I_{ON}$ was $5.27{\times}10^{-7}A$, and S.S was 2.09 V/decade. This degradation of electrical properties was mainly due to increased interfacial and bulk trap densities of forming grain boundaries caused by the annealing treatment.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.9 no.3
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• pp.303-308
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• 1999

As a semiconductor material for electronic devices operated under extreme environmental conditions, silicon carbides(SiCs) have been intensively studied because of their excellent electrical, thermal and other physical properties. The growth characteristics of single-crystalline 4H-SiC homoepitaxial layers grown by a thermal chemical vapor deposition (CVD) were investigated. Especially, the successful growth condition of 4H-SiC homoepitaxial layers using a SiC-uncoated atmospheric pressure chamber and carried out using off-oriented substrates prepared by a modified Lely method. In order to investigate the crystallinity of grown epilayers, Nomarski optical microscopy, Raman spectroscopy, photoluninescence(PL), scanning electron microscopy(SEM) and other techniques were utilized. The best quality of 4H-SiC homoepitaxial layers was observed in conditions of growth temperature $1500^{\circ}C$ and C/Si flow ratio 2.0 of $C_{3}H_{8}\;0.2\;sccm\;&\;SiH_{4}\;0.3\;sccm$. The growth rate of epilayers was about $1.0\mu\textrm{m}/h$ in the above growth condition.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2006.10a
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• pp.170-173
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• 2006

Ferroelectric $Bi_{3.35}Sm_{0.65}Ti_3O_{12}(BST)$ thin films were deposited on $Pt(111)/Ti/SiO_2/Si(100)$ substrates by a sol-gel spin-coating process. In this experiments, $Bi(TMHD)_3$, $Sm_5(O^iPr)_{13}$, $Ti(O^iPr)_4$ were used as precursors, which were dissolved in 2-methoxyethanol. Thereafter, the thin films with the thickness, of 240nm were annealed from 600 to $720^{\circ}C$ in oxygen atmosphere for 1 hr, and post-annealed in oxygen atmosphere for 1 hr after deposition of Pt electrode to enhance the electrical properties. The remanent polarization and coercive voltage of the BST thin films annealed at $720^{\circ}C$ were $19.48\;{\mu}C/cm^2$ and 3.40 V, respectively, and a fatigue-free characteristics. As a result, Sm-substituted bismuth titanate films with good ferroelectric properties and excellent fatigue resistance are useful candidates for ferroelectric memory applications.