• Title/Summary/Keyword: Si-wafer

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Electrolyzed Water Cleaning for Semiconductor Manufacturing (전리수를 이용한 반도체 세정 공정)

  • 류근걸;김우혁;이윤배;이종권
    • Journal of the Semiconductor & Display Technology
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    • v.2 no.3
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    • pp.1-6
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    • 2003
  • In the rapid changes of the semiconductor manufacturing technologies for early 21st century, it may be safely said that a kernel of terms is the size increase of Si wafer and the size decrease of semiconductor devices. As the size of Si wafers increases and semiconductor device is miniaturized, the units of cleaning processes increase. A present cleaning technology is based upon RCA cleaning which consumes vast chemicals and ultra pure water (UPW) and is the high temperature process. Therefore, this technology gives rise to environmental issue. To resolve this matter, candidates of advanced cleaning processes have been studied. One of them is to apply the electrolyzed water. In this work, electrolyzed water cleaning was compared with various chemical cleaning, using Si wafer surfaces by changing cleaning temperature and cleaning time, and especially, concentrating upon the contact angle. It was observed that contact angle on surface treated with Electrolyzed water cleaning was $4.4^{\circ}$ without RCA cleaning. Amine series additive of high pKa (negative logarithm of the acidity constant) was used to observe the property changes of cathode water.

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Direct Bonding of Heterogeneous Insulator Silicon Pairs using Various Annealing Method (열처리 방법에 따른 이종절연층 실리콘 기판쌍의 직접접합)

  • 송오성;이기영
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.16 no.10
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    • pp.859-864
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    • 2003
  • We prepared SOI(silicon-on-insulator) wafer pairs of Si II SiO$_2$/Si$_3$N$_4$ II Si using wafer direct bonding with an electric furnace annealing(EFA), a fast linear annealing(FLA), and a rapid thermal annealing(RTA), respectively, by varying the annealing temperatures at a given annealing process. We measured the bonding area and the bonding strength with processes. EFA and FLA showed almost identical bonding area and theoretical bonding strength at the elevated temperature. RTA was not bonded at all due to warpage, We report that FLA process was superior to other annealing processes in aspects of surface temperature, annealing time, and bonding strength.

Nanotribological characteristics of silicon surfaces modified by IBAD (IBAD로 표면개질된 실리콘표면의 나노 트라이볼로지적 특성)

  • 윤의성;박지현;양승호;공호성;장경영
    • Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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    • 2001.06a
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    • pp.127-134
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    • 2001
  • Nano adhesion and friction between a Sj$_3$N$_4$ AFM tip and thin silver films were experimentally studied. Tests were performed to measure the nano adhesion and friction in both AFM(atomic force microscope) and LFM(lateral force microscope) modes in various ranges of normal load. Thin silver films deposited by IBAD (ion beam assisted deposition) on Si-wafer (100) and Si-wafer of different surface roughness were used. Results showed that nano adhesion and friction decreased as the surface roughness increased. When the Si surfaces were coated by pure silver, the adhesion and friction decreased. But the adhesion and friction were not affected by the thickness of IBAD silver coating. As the normal force increased, the adhesion forces of bare Si-wafer and IBAD silver coating film remained constant, but the friction forces increased linearly. Test results suggested that the friction was mainly governed by the adhesion as long as the normal load was low.

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The Selection on the Optimal Condition of Si-wafer final Polishing by Combined Taguchi Method and Respond Surface Method (실험계획법을 적용한 웨이퍼 폴리싱의 최적 조건 선정에 관한 연구)

  • Won, Jong-Koo;Lee, Jung-Hun;Lee, Jung-Taik;Lee, Eun-Sang
    • Transactions of the Korean Society of Machine Tool Engineers
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    • v.17 no.1
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    • pp.21-28
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    • 2008
  • The final polishing process is based on slurry, pad, conditioner, equipment. Therefore, the concept of wafer final polishing is also necessary for repeatability of results between polished wafers. In this study, the machining conditions have a pressure, table speed, machining time and slurry ratio. This research investigated the surface characteristics that apply variable machining conditions and response surface methodology was used to obtain more flexible and optimumal condition base on Taguchi method. On the base of estimated response surface curvature from the equation and results of Taguchi method, combined design of experiment was considered to lead to optimumal condition. Finally, polished wafer was obtained mirror like surface.

Effects of Package Induced Stress on MEMS Device and Its Improvements (패키징으로 인한 응력이 MEMS 소자에 미치는 영향 분석 및 개선)

  • Choa Sung-Hoon;Cho Yong Chul;Lee Moon Chul
    • Journal of the Korean Society for Precision Engineering
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    • v.22 no.11 s.176
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    • pp.165-172
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    • 2005
  • In MEMS (Micro-Electro-Mechanical System), packaging induced stress or stress induced structure deformation becomes increasing concerns since it directly affects the performance of the device. In the decoupled vibratory MEMS gyroscope, the main factor that determines the yield rate is the frequency difference between the sensing and driving modes. The gyroscope, packaged using the anodic bonding at the wafer level and EMC (epoxy molding compound) molding, has a deformation of MEMS structure caused by thermal expansion mismatch. This effect results in large distribution in the frequency difference, and thereby a lower yield rate. To improve the yield rate we propose a packaged SiOG (Silicon On Glass) process technology. It uses a silicon wafer and two glass wafers to minimize the wafer warpage. Thus the warpage of the wafer is greatly reduced and the frequency difference is more uniformly distributed. In addition. in order to increase robustness of the structure against deformation caused by EMC molding, a 'crab-leg' type spring is replaced with a semi-folded spring. The results show that the frequency shift is greatly reduced after applying the semi-folded spring. Therefore we can achieve a more robust vibratory MEMS gyroscope with a higher yield rate.

Stress Evolution with Annealing Methods in SOI Wafer Pairs (열처리 방법에 따른 SOI 기판의 스트레스변화)

  • Seo, Tae-Yune;Lee, Sang-Hyun;Song, Oh-Sung
    • Korean Journal of Materials Research
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    • v.12 no.10
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    • pp.820-824
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    • 2002
  • It is of importance to know that the bonding strength and interfacial stress of SOI wafer pairs to meet with mechanical and thermal stresses during process. We fabricated Si/2000$\AA$-SiO$_2$ ∥ 2000$\AA$-SiO$_2$/Si SOI wafer pairs with electric furnace annealing, rapid thermal annealing (RTA), and fast linear annealing (FLA), respectively, by varying the annealing temperatures at a given annealing process. Bonding strength and interfacial stress were measured by a razor blade crack opening method and a laser curvature characterization method, respectively. All the annealing process induced the tensile thermal stresses. Electrical furnace annealing achieved the maximum bonding strength at $1000^{\circ}C$-2 hr anneal, while it produced constant thermal tensile stress by $1000^{\circ}C$. RTA showed very small bonding strength due to premating failure during annealing. FLA showed enough bonding strength at $500^{\circ}C$, however large thermal tensile stress were induced. We confirmed that premated wafer pairs should have appropriate compressive interfacial stress to compensate the thermal tensile stress during a given annealing process.

Effect of SC-1 Cleaning to Prevent Al Diffusion for Ti Schottky Barrier Diode (Ti 쇼트키 배리어 다이오드의 Al 확산 방지를 위한 SC-1 세정 효과)

  • Choi, Jinseok;Choi, Yeo Jin;An, Sung Jin
    • Korean Journal of Materials Research
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    • v.31 no.2
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    • pp.97-100
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    • 2021
  • We report the effect of Standard Clean-1 (SC-1) cleaning to remove residual Ti layers after silicidation to prevent Al diffusion into Si wafer for Ti Schottky barrier diodes (Ti-SBD). Regardless of SC-1 cleaning, the presence of oxygen atoms is confirmed by Auger electron spectroscopy (AES) depth profile analysis between Al and Ti-silicide layers. Al atoms at the interface of Ti-silicide and Si wafer are detected, when the SC-1 cleaning is not conducted after rapid thermal annealing. On the other hand, Al atoms are not found at the interface of Ti-SBD after executing SC-1 cleaning. Al diffusion into the interface between Ti-silicide and Si wafer may be caused by thermal stress at the Ti-silicide layer. The difference of the thermal expansion coefficients of Ti and Ti-silicide gives rise to thermal stress at the interface during the Al layer deposition and sintering processes. Although a longer sintering time is conducted for Ti-SBD, the Al atoms do not diffuse into the surface of the Si wafer. Therefore, the removal of the Ti layer by the SC-1 cleaning can prevent Al diffusion for Ti-SBD.

Analysis of Optical Process Depending On Texturing Process of Si Wafer (실리콘 웨이퍼의 표면조직화에 따른 광학적 특성분석)

  • Oh, Teresa
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.11
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    • pp.2439-2443
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    • 2011
  • To obtain the effect of texturing process in Solar cells, the Si-wafers were textured by using the IPA+DI water mixed etching solution with KOH alkaline. All samples were analyzed by the scanning electron microscopy for the surface images, and it was researched the correlation between the efficiency of optical properties and the effect of texturing. From the results of the surface images obtained by SEM, mc-Si wafer shows a isotropic surface but sc-Si wafers displays the unisotropic surface. The reflectance was improved at the sc-Si wafer textured uniformly, and the reflectance of over etched-samples increased.