• Journal of the Microelectronics and Packaging Society
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• v.25 no.2
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• pp.49-53
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• 2018

Recently, technologies for integrating various devices such as a flexible device, a transparent device, and a MEMS device have been developed. The key processes of heterogeneous device manufacturing technology are chip or wafer-level bonding process, substrate grinding process, and thin substrate handling process. In this study, the effect of Si substrate grinding process on the electrical properties of tin oxide thin films applied as transparent thin film transistor or flexible electrode material was investigated. As the Si substrate thickness became thinner, the Si d-spacing decreased and strains occurred in the Si lattice. Also, as the Si substrate thickness became thinner, the electric conductivity of tin oxide thin film decreased due to the lower carrier concentration. In the case of the thinner tin oxide thin film, the electrical conductivity was lower than that of the thicker tin oxide thin film and did not change much by the thickness of Si substrate.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1182-1184
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• 2006

A mica has been introduced as a new substrate material for the fabrication of the poly-Si TFTs. A poly-Si film is produced on the mica substrate at $550^{\circ}C$ by the nickel-induced crystallization and the poly-Si TFTs on the mica substrate are successfully fabricated for the first time.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.3
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• pp.67-71
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• 2014

An attempt to grow high quality GaN on silicon substrate using metal organic chemical vapor deposition (MOCVD), herein GaN epitaxial layers were grown on various Si(111) substrates. Thin Platinum layer was deposited on Si(111) substrate using sputtering, followed by thermal annealing to form Pt nano-clusters which act as masking layer during dry-etched with inductively coupled plasma-reactive ion etching to generate nano-patterned Si(111) substrate. In addition, micro-patterned Si(111) substrate with circle shape was also fabricated by using conventional photo-lithography technique. GaN epitaxial layers were subsequently grown on micro-, nano-patterned and conventional Si (111) substrate under identical growth conditions for comparison. The GaN layer grown on nano-patterned Si (111) substrate shows the lowest crack density with mirror-like surface morphology. The FWHM values of XRD rocking curve measured from symmetry (002) and asymmetry (102) planes are 576 arcsec and 828 arcsec, respectively. To corroborate an enhancement of the growth quality, the FWHM value achieved from the photoluminescence spectra also shows the lowest value (46.5 meV) as compare to other grown samples.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.202-205
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• 2002

Polycrystalline silicon thin film transistors (poly-Si TFTs) are used in a wide variety of applications, and will figure prominently future high-resolution, high-performance flat panel display technology However, it was very difficult to fabricate high performance poly-Si TFTs at a temperature lower than 300$^{\circ}C$ for glass substrate. Conventional process on a glass substrate were limited temperature less than 600$^{\circ}C$ This paper proposes a high temperature process above 750$^{\circ}C$ using a flexible molybdenum substrate deposited hydrogenated amorphous silicon (a-Si:H) and than crystallized a rapid thermal processor (RTP) at the various temperatures from 750$^{\circ}C$ to 1050$^{\circ}C$. The high temperature annealed poly-Si film illustrated field effect mobility higher than 30 $\textrm{cm}^2$/Vs, achieved I$\sub$on//I$\sub$off/ current ratio of 10$^4$ and crystall volume fraction of 92%. In this paper, we introduce the new TFTs Process as flexible substrate very promising roll-to-roll process, and exhibit the properties of high temperature crystallized poly-Si Tn on molybdenum substrate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.481-485
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• 2003

Amorphous silicon (a-Si:H) based TFT process has been studied at the maximum temperature of 15$0^{\circ}C$ with 25${\mu}{\textrm}{m}$ thick flexible and adhesive tape type polyimide foil substrate, which has benefit on handling a rugged, flexible plastic substrate trough sticking simply it to glass. This paper summarize the process procedure of the TFT on the plastic substrate and shows its electrical characteristics in comparison with glass substrate using primarily the ON/OFF current ratio and the field effect mobility as the quality criterion. The a-SiN:H coating layer played an important role in decreasing surface roughness of plastic substrate, so leakage current of TFT was decreased and mobility was increased. The results show that high quality a-Si:H TFTs can be fabricated on the plastic substrates through coating a rough plastic surface with a-SiN:H.

• Journal of the Korean Ceramic Society
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• v.35 no.3
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• pp.259-263
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• 1998

WSi2/CVD-Si/SiO2/Si-substrate의 폴리사이드 구조에서 실리콘 증착 POCl3 확산 그리고 WSi2 증착 유무에 따른 Thin oxide 특성을 연구했다 WSi2 막을 증착하지 않은 CVD-Si/SiO2/Si-substrate 구조에서 CVD-Si을 po-lycrystalline-Si으로 증착한 시편이 amorphous-Si을 증착한 시편보다 산화막 불량이 적다 WSi2 를 증착시킨 WSi2/CVD-Si/SiO2./Si-substrate의 구조에서 CVD-Si의 polycrystalline-Si 혹든 amorphous-Si 의 막 증착에 따른 thin oxide의 불량율 차이는 미미하다 산화막 불량은 CVD-Si에 확산시킨 인(P) 증가 즉 면저항(sheet resistance) 감소로 증가한다. Thin oxide의 절연특성은 WSi2 증착으로 저하된다 WSi2 증착으로 산화막 두께는 증가하나 막 특성은 열등해져 산화막 절연성이 떨어진다.

• Korean Journal of Metals and Materials
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• v.47 no.5
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• pp.322-329
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• 2009

60 nm- and 20 nm-thick hydrogenated amorphous silicon (a-Si:H) layers were deposited on 200 nm $SiO_2/Si$ substrates using ICP-CVD (inductively coupled plasma chemical vapor deposition). A 10 nm-Ni layer was then deposited by e-beam evaporation. Finally, 10 nm-Ni/60 nm a-Si:H/200 nm-$SiO_2/Si$ and 10 nm-Ni/20 nm a-Si:H/200 nm-$SiO_2/Si$ structures were prepared. The samples were annealed by rapid thermal annealing for 40 seconds at $200{\sim}500^{\circ}C$ to produce $NiSi_x$. The resulting changes in sheet resistance, microstructure, phase, chemical composition and surface roughness were examined. The nickel silicide on a 60 nm a-Si:H substrate showed a low sheet resistance at T (temperatures) >$450^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate showed a low sheet resistance at T > $300^{\circ}C$. HRXRD analysis revealed a phase transformation of the nickel silicide on a 60 nm a-Si:H substrate (${\delta}-Ni_2Si{\rightarrow}{\zeta}-Ni_2Si{\rightarrow}(NiSi+{\zeta}-Ni_2Si)$) at annealing temperatures of $300^{\circ}C{\rightarrow}400^{\circ}C{\rightarrow}500^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate had a composition of ${\delta}-Ni_2Si$ with no secondary phases. Through FE-SEM and TEM analysis, the nickel silicide layer on the 60 nm a-Si:H substrate showed a 60 nm-thick silicide layer with a columnar shape, which contained both residual a-Si:H and $Ni_2Si$ layers, regardless of annealing temperatures. The nickel silicide on the 20 nm a-Si:H substrate had a uniform thickness of 40 nm with a columnar shape and no residual silicon. SPM analysis shows that the surface roughness was < 1.8 nm regardless of the a-Si:H-thickness. It was confirmed that the low temperature silicide process using a 20 nm a-Si:H substrate is more suitable for thin film transistor (TFT) active layer applications.

• Korean Journal of Materials Research
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• v.22 no.9
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• pp.450-453
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• 2012

In crystalline solar cells, the substrate itself constitutes a large portion of the fabrication cost as it is derived from semiconductor ingots grown in costly high temperature processes. Thinner wafer substrates allow some cost saving as more wafers can be sliced from a given ingot, although technological limitations in slicing or sawing of wafers off an ingot, as well as the physical strength of the sliced wafers, put a lower limit on the substrate thickness. Complementary to these economical and techno-physical points of view, a device operation point of view of the substrate thickness would be useful. With this in mind, BC-BJ Si and GaAs solar cells are compared one to one by means of the Medici device simulation, with a particular emphasis on the substrate thickness. Under ideal conditions of 0.6 ${\mu}m$ photons entering the 10 ${\mu}m$-wide BC-BJ solar cells at the normal incident angle (${\theta}=90^{\circ}$), GaAs is about 2.3 times more efficient than Si in terms of peak cell power output: 42.3 $mW{\cdot}cm^{-2}$ vs. 18.2 $mW{\cdot}cm^{-2}$. This strong performance of GaAs, though only under ideal conditions, gives a strong indication that this material could stand competitively against Si, despite its known high material and process costs. Within the limitation of the minority carrier recombination lifetime value of $5{\times}10^{-5}$ sec used in the device simulation, the solar cell power is known to be only weakly dependent on the substrate thickness, particularly under about 100 ${\mu}m$, for both Si and GaAs. Though the optimum substrate thickness is about 100 ${\mu}m$ or less, the reduction in the power output is less than 10% from the peak values even when the substrate thickness is increased to 190 ${\mu}m$. Thus, for crystalline Si and GaAs with a relatively long recombination lifetime, extra efforts to be spent on thinning the substrate should be weighed against the expected actual gain in the solar cell output power.

• Applied Microscopy
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• v.24 no.4
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• pp.123-131
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• 1994

In this study the initial stage nucleation and growth of Ni silicide on (001) Si by evaporation and furnace annealing have been investigated by transmission electron microscopy. The pressure was $10^{-6}$ Torr during evaporation and annealing. And the annealing temperature to produce $NiSi_2\;was\;800^{\circ}C$. From the evaporated film, $NiSi_2$ nucleus has grown into Si substrate with an epitaxial orientation relationship. Interfaces between $NiSi_2$ and Si were A-type {111} interfaces and {100} $NiSi_2$ interfaces were also observed at the initial stage of nucleation. Ni silicide grew into Si substrate, but the nucleus partly grew into the evaporated film, with no facets, from the nuclei in the Si substrate. $NiSi_2$ nucleus with (111) habit planes was also observed.

• Proceeding of EDISON Challenge
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• 2014.03a
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• pp.415-419
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• 2014

나노스케일 MOSFET에서 leakage current는 중요한 이슈로서 $Si_{1-x}Ge_x$ alloy를 substrate로 사용할 경우 leakage current에 어떤 영향을 미칠 것인지 시뮬레이션을 통하여 알아보았다. $Si_{1-x}Ge_x$ alloy에서 Ge의 비율이 증가할수록 유효질량이 작아졌으나 conduction band minimum의 위치는 Si에 비해 상승하였다. 이로 인해 tunneling 확률이 증가하여 $Si_{1-x}Ge_x$ alloy를 substrate로 사용할 경우 leakage current를 더욱 증가시키게 되었다.