• 대한전자공학회논문지SD
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• 제40권12호
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• pp.24-30
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• 2003

본 논문에서는 첨두 검출기의 구조를 개선함으로써 정착시간(settling time)을 더욱 단축시킬 수 있는 적응형 기준레벨자동 발생회로를 제안했다. 제안한 기준레벨 자동 발생회로에 대해 비슷한 정착시간을 설정하였을 때에 오차전압비율이 기존 구조에 비해 절반 이하로 줄일 수 있어 정착시간을 상당량 개선할 수 있음을 해석을 통해 밝혔다. 아울러 상용 파운드리(foundry)를 이용하여 1.25G EPON 시스템용 버스트 모드기준레벨 자동 발생회로를 설계한 결과 동적 영역(dynamic range)이 40㏈인 입력신호에 대해 6㎱ 라는 매우 짧은 시간 이내에 기준 레벨을 생성해 내는 결과를 얻을 수 있었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.492-492
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• 2014

On account of the good conductivity and optical properties, TCO is generally used in silicon heterojunction solar cell since the emitter material, hydrogenated amorphous silicon (a-Si:H), of the solar cell has low conductivity compare to the emitter of crystalline silicon solar cell. However, the work function mismatch between TCO layer and emitter leads to band-offset and interfere the injection of photo-generated carriers. In this study, work function engineering of TCO by oxygen reactive sputtering method was carried out to identify the trend of band-offset change. The open circuit voltage and short circuit current are noticeably changed by work function that effected from variation of oxygen ratio.

• 한국전기전자재료학회논문지
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• 제20권11호
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• pp.995-999
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• 2007

We investigated the characteristics of a flux-lock type superconducting fault current limiter(SFCL) considering magnetization characteristic of iron core. The flux-lock type SFCL, like other types of SFCLs using the iron core, undergoes the saturation of the iron core during the initial fault time. Therefore, if the design to prevent the saturation of the iron core is considered, the effective fault current limiting operation can be achieved. Through the analysis for its equivalent circuit including the magnetization characteristic of the iron core, the limiting impedance of the flux-lock type SFCL was drawn. The magnetization currents and the limited currents of SFCL, which were dependent on the winding direction and the turns' ratio between two coils, were investigated from the short circuit experiment. It was confirmed that their experimental results agreed with the analysis ones.

• 한국태양에너지학회:학술대회논문집
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• 한국태양에너지학회 2011년도 춘계학술발표대회 논문집
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• pp.293-298
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• 2011

The most widely used method to form an electrode in industrial solar cells are screen printing. Screen printing is characterized by a relatively simple and well-known production sequence with high throughput rates. However the method is difficult to implement a fine line width of high-efficiency solar cells can not be made. The open circuit voltage(Voc) and the short circuit current density(Jsc) and fill factor(FF) need to be further improved to increase the efficiency of silicon solar cells. In this study, gravure offset printing method using the multicrystalline-silicon solar cells were fabricated. Gravure off-set printing method which can print the fine line width of finger electrode can have the ability reduce the shaded area and increase the Jsc. Moreover it can make a high aspect ratio thereby series resistance is reduced and FF is increased. Approximately $50{\mu}m$ line width with $35{\mu}m$ height was achieved. The efficiency of gravure off set was 0.7% higher compare to that of scree printing method.

• Current Photovoltaic Research
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• 제11권3호
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• pp.67-74
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• 2023

The earth-abundant element-based Cu₂ZnSn(S,Se)₄ (CZTSSe) thin film solar cells (TFSCs) have attracted greater attention in the photovoltaic (PV) community due to their rapid development in device power conversion efficiency (PCE) >13%. In the present work, we demonstrated the fine-tuning of the bandgap in the CZTSSe TFSCs by altering the sulfur (S) to the selenium (Se) chalcogenide ratio. To achieve this, the CZTSSe absorber layers are fabricated with different S/(S+Se) ratios from 0.02 to 0.08 of their weight percentage. Further compositional, morphological, and optoelectronic properties are studied using various characterization techniques. It is observed that the change in the S/(S+Se) ratios has minimal impact on the overall Cu/(Zn+Sn) composition ratio. In contrast, the S and Se content within the CZTSSe absorber layer gets altered with a change in the S/(S+Se) ratio. It also influences the overall absorber quality and gets worse at higher S/(S+Se). Furthermore, the device performance evaluated for similar CZTSSe TFSCs showed a linear increase and decrease in the open circuit voltage (V_oc) and short circuit current density (J_sc) of the device with an increasing S/(S+Se) ratio. The external quantum efficiency (EQE) measured also exhibited a linear blue shift in absorption edge, increasing the bandgap from 1.056 eV to 1.228 eV, respectively.

• Journal of Advanced Marine Engineering and Technology
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• 제21권4호
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• pp.387-392
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• 1997

This paper describes a combination surge generator for carrying out performance tests on the surge protection circuits of shipboard electrical systems. Pspice simulations were performed to decide the values of the parts required and to analyze the characteristics of the generator circuitry. The surge generator fabricated can produce four of the most common surge test waveforms : the O.5i/S/100kHz Ringwave, the 1.2/50$\mu$S voltage, the 8/20$\mu$S current, and the lO/lOOOi/S voltage wave¬forms specified in ANSI Std. C62. Source impedances of the surge generator are 12$\Omega$ in the O.5$\mu$S/100kHz mode, O.5$\Omega$ in the 1.2/50$\mu$S and 8/20$\mu$S mode, and 40$\Omega$in the l0/1000$\mu$S mode, and are determined by the ratio of the maxi¬mum open - circuit voltage to the maximum short - circuit current. Experimental results show that the surge generator provides most of the outputs required for the testing of the surge protection circuits on shipboard electrical systems.

• 한국전기전자재료학회논문지
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• 제24권5호
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• pp.410-415
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• 2011

In this paper, we investigated the fault current limiting and the load voltage sag suppressing characteristics of the flux-lock type SFCL, designed with the additive polarity winding, according to the variations of turn number's ratio and the comparative analysis between the resistive type and the flux-lock type SFCLs were performed as well. From the analysis for the short-circuit tests, the flux-lock type SFCL designed with the larger turn number's ratio was shown to perform more effective fault current limiting and load voltage sag suppressing operations compared to the flux-lock type SFCL designed with the lower turn number's ratio through the fast quench occurrence of the high-$T_C$ superconducting (HTSC) element comprising the flux-lock type SFCL. In addition, the recovery time of the flux-lock type SFCL after the fault removed could be confirmed to be shorter in case of the flux-lock type SFCL designed with the lower turn number ratio.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.1110-1111
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• 2008

The life time of PV module is semi-permanent. But, because of installation and module fabrication process, its important part can not be finished. In this paper, we analyze 15 years old modules made from different company. Among the PV modules, the maximum power drop ratio was 12.23% minimum and 80.63% maximum. Also the effect of solar cell's short circuit current difference was analyzed. The PV module exposed about 65days, its the maximum power drop ratio was 1.29% minimum and 23.43% maximum. It is for reduction of current value. And the reason for current reduction was due to reduction of parallel resistance of solar cell. To prevent early degradation, it is need to have attention to fabrication, installation and maintenance.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.134-142
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• 2010

A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 하계학술대회 논문집 A
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• pp.535-538
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• 1994

In this paper, an isolated ZVS-PWM boost converter is proposed for single stage line conversion. For power factor correction, we used the half bridge topology at the primary side of isolation transformer permitting switching devices to operate under ZVS by using circuit parastics and operating at a fixed duty ratio near 50%. Thus the relatively continuous input current distortion and small size input filter are also achievable. The ZVS-PWM boost operation of the proposed converter can be achieved by using the boost inductor $L_f$, main switch $Q_3$, and simple auxiliary circuit at the secondary side of isolation transformer. The secondary side circuit differ from a conventional PWM boost converter by introduction a simple auxiliary circuit. The auxiliary circuit is actived only during a short switching transition time to create the ZVS condition for the main switch as that of the ZVT-PWM boost converter. With a single stage, it is possible to achieve a sinusoidal line current at unity power factor as well as the isolated 48V DC output. Comparing to the two stage schemes, overall effiency of the proposed converter is highly improved due to the effective ZVS of all devices as well as single stage power conversion. Thus, it can be operated at high switching frequency allowing use of small size input filter. Minimum voltage and current stress make it high power application possible.