• 전기학회논문지
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• 제65권6호
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• pp.955-961
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• 2016

Fault location estimation is an important element for rapid recovery of power system when fault occur in transmission line. In order to calculate line impedance, most of fault location algorithm uses by measuring relaying waveform using DFT. So if there is a calculation error due to the influence of phasor by DC offset component, due to large vibration by line impedance computation, abnormal and non-operation of fault locator can be issue. It is very important to implement the robust fault location algorithm that is not affected by DC offset component. This paper describes an enhanced fault location algorithm based on the DC offset elimination filter to minimize the effects of DC offset on a long transmission line. The proposed DC offset elimination filter has not need any erstwhile information. The phase angle delay of the proposed DC offset filter did not occurred and the gain error was not found. The enhanced fault location algorithm uses DFT filter as well as the proposed DC offset filter. The behavior of the proposed fault location algorithm using off-line simulation has been verified by data about several fault conditions generated by the ATP simulation program.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.335-336
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• 2008

Overhead transmission lines are mainly crossing mountainous area. They are easily affected in weathers like typhoon, strong wind, lightning, heavy rain, or heavy snow. Sometimes these weathers cause transmission line faults. A lightning flashover is most often fault. Nowadays lightning density in KOREA is growing high and lightning flashovers occur more often. A lightning flashover on transmission line is mostly cleared by momentary operation of a circuit breaker, so power failure happens rarely. However, when both circuits trip simultaneously due to the lightning flashovers on double circuit transmission line, short time power failure and voltage drop happen. KEPCO has used transmission line arresters to avoid double circuit simultaneous trip out since 2003. And transmission line arresters cannot be installed with KEPCO's present metal fittings, so various fittings have been used for each transmission line arrester manufacturer. This paper introduces development and standardization of arc-horn and metal fittings for transmission line arrester which can be used for both existing lines and new lines in KEPCO.

• 한국정밀공학회지
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• 제20권4호
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• pp.92-102
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• 2003

To detect electrical faults of a TFT (Thin Film Transistor) panel for the LCD (Liquid Crystal Display), techniques of converting electric field to an image are used One of them is the PDLC (polymer-dispersed liquid crystal) modulator which changes light transmittance under electric field. The advantage of PDLC modulator in the electric field detection is that it can be used without physically contacting the TFT panel surface. Specific pattern signals are applied to the data and gate electrodes of the panel to charge the pixel electrodes and the image sensor detects the change of transmittance of PDLC positioned in proximity distance above the pixel electrodes. The image represents the status of electric field reflected on the PDLC so that the characteristic of the PDLC itself plays an important role to accurately quantify the defects of TFT panel. In this paper, the image of the PDLC modulator caused by the change of electric field of the pixel electrodes on the TFT panel is acquired and how the characteristics of PDLC reflect the change of electric field to the image is analyzed. When the holding time of PDLC is short, better contrast of electric field image can be obtained by changing the instance of applying the driving voltage to the PDLC.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권4호
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• pp.243-250
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• 2005

Test methodology is diversity by devices and the number of test pattern is tremendous because the digital circuit includes TTL and CMOS family ICs as well as high density devices such as ROM and RAM. Accordingly, the quick and effective test strategy is required to enhance the test productivity. This paper proposes the test strategy which is able to be applied efficiently to the diversity devices on the digital circuit board by analyzing the structure and characteristic of the digital device. Especially, this test strategy detects the faulted digital device or the faulted digital circuit on the digital board using SSA(Serial Signature Analysis) technique based on the polynomial division theory The SSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Register) representing the characteristic equation. Also, the method to obtain the optimal signature analysis circuit is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• 조명전기설비학회논문지
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• 제19권2호
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• pp.131-137
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• 2005

보호계전기는 고장에 의해 파생되는 단락$\cdot$지락 사고로부터 전력 시스템을 보호하기 위하여 널리 사용되고 있다. 전통적으로 디지털보호계전기는 디지털신호처리 프로세서 혹은 마이크로프로세서로 구현되는데 본 연구는 이를 고성능$\cdot$고효율$\cdot$다기능의 단일칩으로 구현하기 위한 하드웨어 설계 기술에 관해 다룬다. 제작된 디지털보호계전기는 FPGA(Field Programmable Gate Array)로 구현하였고 16KSPS이상의 처리 성능을 가지며 평균 오차율 $0.03(\%)$미만으로 보호계전알고리즘을 수행할 수 있다.

• 한국시뮬레이션학회논문지
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• 제12권3호
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• pp.69-81
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• 2003

To manage a cluster of distributed server systems, a number of management aspects should be considered in terms of configuration management, fault management, performance management, and user management. System performance monitoring and reporting take an important role for performance and fault management. In this paper, we present distributed system architecture modeling of a performance monitoring and reporting tool. Modeling architecture of four subsystems are introduced: node agent, data collection, performance management & report, and DB schema. The performance-related information collected from distributed servers are categorized into performance counters, event data for system status changes, service quality, and system configuration data. In order to analyze those performance information, we use a number of ways to evaluate data corelation. By using some results from a real site of a company and from simulation of artificial workload, we show the example of performance collection and analysis. Since our report tool detects system fault or node component failure and analyzes performances through resource usage and service quality, we are able to provide information for server load balancing, in short term view, and the cause of system faults and decision for system scale-out and scale-up, in long term view.

• 대한전기학회논문지:전력기술부문A
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• 제54권11호
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• pp.525-532
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• 2005

This paper presents a new two-terminal numerical algorithm for fault location estimation and for faults recognition using the synchronized phaser in time-domain. The proposed algorithm is also based on the synchronized voltage and current phasor measured from the assumed PMUs(Phasor Measurement Units) installed at both ends of the transmission lines. Also the arc voltage wave shape is modeled numerically on the basis of a great number of arc voltage records obtained by transient recorder. From the calculated arc voltage amplitude it can make a decision whether the fault is permanent or transient. In this paper the algorithm is given and estimated using DFT(discrete Fourier Transform) and the LES(Least Error Squares Method). The algorithm uses a very short data window and enables fast fault detection and classification for real-time transmission line protection. To test the validity of the proposed algorithm, the Electro-Magnetic Transient Program(EMTP/ATP) is used.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 C
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• pp.1056-1058
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• 1998

Voltage dips caused by transmission system faults are usually of a short duration. High speed relaying and breaker operation will typically limit the disturbance to 0.1 seconds. Most motor controllers obtain their control power directly from the bus by means of a control transformer. Under this condition, a voltage dip can cause the contactor to drop out. disconnecting the motor from the line. The rapid re-energizing of the controller is in effect a fast reclosure which may result in motor damage. The time delay re-energizing of controller will result in a greater loss of speed and possibly loss of stability. Other means of controller can be used to prevent the motor from being disconnected from line during the fault. This can be accomplished by DC power controller or mechanically latched controller. This paper demonstrates that DC power controller or mechanically latched type controller to prevent the motor from being disconnected from line during the fault is, the most effective in minimizing speed reduction, transient motor current, transient motor torque and transient shaft torque by EMTP calculation.

• 반도체디스플레이기술학회지
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• 제12권2호
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• pp.67-72
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• 2013

Temperature is a critical parameter in yield improvement for wafer manufacturing. In chemical vapor deposition (CVD) equipment, crack defect in ceramic heater leads to yield reduction, however, there is no suitable ceramic heater fault detection system for conventional CVD equipment. This paper proposes a short-time zero-crossing rate based fault detection method for the ceramic heater in CVD equipment. The proposed method measures the output signal ($V_{pp}$) of RF filter and extracts the zero-crossing rate (ZCR) as feature vector. The extracted feature vectors have a discriminant power and Gaussian mixture model (GMM) based fault detection method can detect fault in ceramic heater. Experimental results, carried out by measured signals provided by a CVD equipment manufacturer, indicate that the proposed method detects effectively faults in various process conditions.

• 대한전자공학회논문지SD
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• 제40권1호
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• pp.61-71
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• 2003

본 논문에서 제안하는 GNS 시퀀스는 SoC 연결 고 장 테스트를 수행할 때 aliasing 고장 증후와 confounding 고장 증후를 고 장 증후를 발생시키지 않는 시퀀스로 연결 고장 위치의 분석을 효과적으로 수행할 수 있다. GNS 시퀀스는 과거 보드 수준의 연결 테스트를 수행하기 위한 IEEE 1149.1 std. 와 유사한 구조로 SoC 의 연결 테스트를 수행하게 되어있는 IEEE P1500 에 적용하여 SoC 내부의 IP 상호간에 존재하는 연결 고장을 검출하고 그 위치를 분석하는데, 이때 입력되는 테스트 시퀀스의 길이가 기른 연구들에 비해 처소의 값을 가짐으로써 연결 테스트 수행 시간을 단축할 수 있는 효과적인 연결 테스트 알고리듬이다.