• Journal of Electrical Engineering and Technology
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• v.12 no.3
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• pp.1137-1145
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• 2017

This paper proposes the dead time effect compensation algorithm using proportional resonant controller in pulse width modulation inverter of motor drive. To avoid a short circuit in the dc link, the dead time of the switch device is surely required. However, the dead time effect causes the phase current distortions, torque pulsations, and degradations of control performance. To solve these problems, the output current including ripple components on the synchronous reference frame and stationary reference frame are analyzed in detail. As a results, the distorted synchronous d-and q-axis currents contain the 6th, 12th, and the higher harmonic components due to the influence of dead time effect. In this paper, a new dead time effect compensation algorithm using proportional resonant controller is also proposed to reduce the output current harmonics due to the dead time and nonlinear characteristics of the switching devices. The proposed compensation algorithm does not require any additional hardware and the offline experimental measurements. The experimental results are presented to demonstrate the effectiveness of the proposed dead time effect compensation algorithm.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.5
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• pp.409-415
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• 2012

This paper presents a new software-based on-line dead-time compensation technique for a single-phase grid-connected photovoltaic (PV) inverter system. To prevent a short circuit in the inverter arms, a switching delay time must be inserted in the pulse width modulation (PWM) signals. This causes the dead-time effect, which degrades the system performance around zero-crossing point of the output current. To reduce the dead-time effect around the zero-crossing point of grid current, a harmonic mitigation of grid current is used as an additional part of the synchronous frame current control scheme. This additional task mitigates the harmonic components caused by the dead-time from the grid current. Simulation and experimental results are shown to verify the effectiveness of the proposed dead-time compensation method in the single-phase grid-connected inverter system.

• Journal of the Korean Society of Safety
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• v.22 no.4
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• pp.26-31
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• 2007

According to the statistical analysis on the electrical fire of 2005 years, most of electrical fire is generated from short circuit(4,985 cases), overcurrent(755 cases) leakage current(391 cases), poor contact(378 cases), disconnection(36 cases) on the electrical wiring device. The researches for the fire hazard about normal electric wiring have already been progressing in the advanced country such as USA and Japan, but Comparative study of the disconnection has not been conducted. Therefore, in this paper, we have simulated the thermal analysis for electrical wire according to deteriorating time in a normal state and disconnection with electrical wire using the electrical-thermal finite element method(Flux 3D). This paper acquire basis data of electricity fire signal by disconnection and wish to help for electrical fire cause diagnosis business.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.706-707
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• 2011

The insertion of the crowbar system in the doubly fed induction generator rotor circuit for a short period of time during grid disturbance enables a more efficient way of limiting transient rotor current and hence protecting the rotor side converter (RSC) and the DC - link capacitor. When crowbar is activated at fault occurrence and clearance time, RSC is blocked while DC -link capacitor and the grid side converter (GSC) can be controlled to provide reactive power support at the PCC and improve the voltage which helps to comply with grid codes. In this paper, control strategies for crowbar system to limit the rotor current during fault is presented with RSC and GSC controllers are modified to control PCC voltage during disturbance to enhance DFIG wind farm to comply with some strict grid codes. Model simulated on MATLAB/Simulink verify the study through simulation results presented.

• International Journal of Contents
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• v.9 no.1
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• pp.38-41
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• 2013

The clamp meter maintains electric safety as a non-invasive method while measuring the absolute value of tube current with it has been recently developed for an X-ray high-tension cable. Especially this can show high accuracy at short X-ray exposure time. Considering such a condition, this study is to evaluate the feasibility of a clamp meter in measuring X-ray tube current by taking the measurements and comparing with those of the Dynalyzer III which has been considered as a standard measuring device. From measuring the tube current accuracy depending on changes in tube voltage and exposure time, the clamp meter showed higher accuracy rate which was -1.3~4.2% difference. Thus clamp meter can be used for clinical radiologists who are not familiar electric circuit to manage X-ray devices easily and correctly in the future.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.128-139
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• 1996

In this paper, we propose an algorithm to solve the problem of placement of rectangular blocks whose sizes and shpaes are pre-determined. The proposed method solves the placement of many retangular blocks of different sizes and shapes in a hierarchical manner, so as to minimize the chip area. The placement problem is divided into several sub-problems: hierarchical partioning, hierarchical area/shape estimation, hierarchical pattern pacement, overlap removal, and module rotation. After the circuit is recursively partitioned to build a hierarchy tree, the necessary wiring area and module shpaes are estimated using the resutls of the partitioning and the pin information before the placement is performed. The placement templaes are defined to represent the relative positions of the modules. The area and the connectivity are optimized separately at each level of hierachy using the placement templates, so the minimization of chip area and wire length can be achieved in a short execution time. Experiments are made on the MCNC building block benchmark circuits and the results are compared with those of other published methods. The proposed technique is shown to produce good figures in tems of execution time and chip area.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.1
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• pp.199-202
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• 2009

Scan design is currently the most widely used structured Design For Testability approach. In scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers(also called scan chains) during the shift operation. As a result, all inputs to the combinational logic, including those driven by scan cells, can be controlled and all outputs from the combinational logic, including those driving scan cells, can be observed. The scan inserted design, called scan design, is operated in three modes: normal mode, shift mode, and capture mode. Circuit operations with associated clock cycles conducted in these three modes are referred to as normal operation, shift operation, and capture operation, respectively. In spite of these, scan design methodology has defects. They are power dissipation problem and test time during test application. We propose a new methodology about scan shift clock operation and present low power scan design and short test time.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.12
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• pp.953-958
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• 2001

The antifuse is a semi-permanent memory device like a ROM which shows the open or short state, and a switch device connecting logic blocks selectively in FPGA. In addition, the antifuse has been used as a logic device to troubleshoot defective memory cells arising from SDRAM processing. In this study, we have fabricated ONO antifuses consisted of PIP structure. The antifuse shows a high resistance more than several G Ω in the normal state, and shows a low resistance less than 500 Ω after program. The program resistance variation according to temperature shows the very stable value of $\pm$20 Ω. At this time, its program voltage shows 6.7∼7.2 V and the program is performed within 1 second. Therefore this result shows that the PIP antifuse is a very stable and programmable logic device.

• Current Photovoltaic Research
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• v.5 no.4
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• pp.105-108
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• 2017

The reactive ion etching (RIE) technology which enables nano-texturatization of surface is applied on monocrystalline silicon solar cell. The additional RIE process on alkalized textured surface further improves the blue response and short circuit current. Such parameter is characterized by surface reflectance and quantum efficiency measurement. By varying the RIE process time and matching the subsequent processes, the absolute efficiency gain of 0.13% is achieved. However, the result indicates potential efficiency gain could be higher due to process integration. The critical etch process time is discussed which minimizes both front surface reflectance and etching damage, considering the challenges of required system throughput in industry.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.176-186
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• 1996

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently, IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. In this paper, G-ATPG (gyeongsang automatic test pattern genrator) is designed which is able to be adapted to IDDQ testing for combinational CMOS VLSI. In G-ATPG, stuck-at, transistor stuck-on, GOS (gate oxide short)or bridging faults which can occur within priitive gate or XOR is modelled to primitive fault patterns and the concept of a fault-sensitizing gate is used to simulate only gates that need to sensitize the faulty gate because IDDQ test does not require the process of fault propagation. Primitive fault patterns are graded to reduce CPU time for the gates in a circuit whenever a test pattern is generated. the simulation results in bench mark circuits show that CPU time and fault coverage are enhanced more than the conventional ATPG using IDDQ test.