• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.189-192
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• 2001

Recently, STI process is getting attention as a necessary technology for making high density of semiconductor by devices isolation method. However, it does have various problems caused by CMP process, such as torn oxide defects, nitride residues on oxide, damages of si active region, contaminations due to post-CMP cleaning, difficulty of accurate end point detection in CMP process, etc. In this work, the various defects induced by CMP process was introduced and the above mentioned Problems of CMP process was examined in detail. Finally, the guideline of future CMP process was presented to reduce the effects of these defects.

• 한국시뮬레이션학회논문지
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• 제11권1호
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• pp.23-30
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• 2002

An STI(Shallow Trench Isolation) by using a CMP(Chemical Mechanical Polishing) process has been one of the key issues in the device isolation[1] In this paper we fabricated N, P-MOSFEET tall analyse hump characteristics in various rounding oxdation thickness(ex : Skip, 500, 800, 1000$\AA$). As a result we found that hump occurred at STI channel edge region by field oxide recess. and boron segregation(early turn on due to boron segregatiorn at channel edge). Therefore we improved that hump occurrence by increased oxidation thickness, and control field oxide recess( 20nm), wet oxidation etch time(19HF,30sec), STI nitride wet cleaning time(99HF, 60sec+P 90min) and fate pre-oxidation cleaning time (U10min+19HF, 60sec) to prevent hump occurring at STI channel edge.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 전자세라믹스 센서 및 박막재료 반도체재료 일렉트렛트 및 응용기술
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• pp.14-17
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• 2000

The rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.18um semiconductor device. To employ in STI CMP, the reverse moat process has been added thus the process became complex and the defects were seriously increased. Removal rates of each thin films in STi CMP was not equal hence the devices must to be effected, that is, the damage was occured in the device dimension in the case of excessive CMP process and the nitride film was remained on the device dimension in the case of insufficient CMP process than these defects affect the device characteristics. We studied the current sensing method in STI-CMP with the reverse moat pattern.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.64-64
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• 2003

고집적화된 시스템 LSI 반도체 소자 제조 공정에서 소자의 고속화 및 고성능화에 따른 배선층수의 증가와 배선 패턴 미세화에 대한 요구가 갈수록 높아져, 광역평탄화가 가능한 STI CMP(Shallow Trench Isolation Chemical-Mechanical-Polishing)공정의 중요성이 더해가고 있다. 이러한 STI CMP 공정에서 세리아 슬러리에 첨가되는 계면활성제의 농도에 따라 산화막과 질화막 사이의 연마 선택비를 제어하는 것이 필수적 과제로 등장하고 있다. 일반적인 CMP 공정에서 압력 증가에 따른 연마 제거량이 Prestonian 거동을 나타내는 반면, 연마 입자의 크기를 변화시켜 계면활성제의 농도를 달리 하였을 경우, 압력 변화에 따라 Non-Prestonian 거동이 나타나는 것을 고찰할 수 있었다. 따라서 본 연구에서는 세리아 슬러리 내에 첨가되는 계면활성 제의 농도와 연마입자의 크기를 달리한 후, 압력을 변화시킴으로 나타나는 non-Prestonian 거동에 미치는 영향에 대하여 연구하였다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.65-65
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• 2003

Chemical mechanical polishing (CMP) is one of the most important processes in recent ULSI (Ultra Large Scale Integrated Circuit) manufacturing technology. Recently, ceria slurries with surfactant have recently been used in STI-CMP,[1] became they have high oxide-to-nitride removal selectivity and widen the processing margin The role of the abrasives, however, on the effect of planarization on STI-CMP is not yet clear. In this study, we investigated how the crystal characteristic affects the planarization efficiency of wafer surface with controlling crystallite size and poly crystalline abrasive size independently.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.54-57
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• 2001

We studied the characteristics of polishing pad, which can apply STI-CMP process for global planarization of multilevel interconnection structure. Also, we investigated the effects of different sets of polishing pad, such as soft and hard pad. As an experimental result, hard pad showed center-fast type, and soft pad showed edge-fast type. Totally, the defect level has shown little difference, however, the counts of scratch was defected less than 2 on JRlll pad. Through the above results, we can select optimum polishing pad, so we can expect the improvements of throughput and devise yield.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.33-36
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• 2001

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The rise throughput and the stability in the device fabrication can be obtained by applying of CMP process to STI structure in 0.18$\mu\textrm{m}$ m semiconductor device. The reverse moat process has been added to employ in of each thin films in STI-CMP was not equal, hence the devices must to be effected, that is, the damage was occurred in the device area for the case of excessive CMP process and the nitride film was remained on the device area for the case of insufficient CMP process, and than, these defects affect the device characteristics. Also, we studied the High Selectivity Slurry(HSS) to perform global planarization without reverse moat step.

• 한국재료학회지
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• 제16권5호
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• pp.308-311
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• 2006

The purpose of this study is to investigate the difference of the wafer nanotopography impact on the oxide-film thickness variation between the STI CMP using ceria slurry and STI CMP using fumed silica slurry. The nanotopography impact on the oxide-film thickness variation after STI CMP using ceria slurry is 2.8 times higher than that after STI CMP using fumed silica slurry. It is attributed that the STI CMP using ceria slurry follows non-Prestonian polishing behavior while that using fumed silica slurry follows Prestonian polishing behavior.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.522-529
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• 2013

In this paper, simple but very effective techniques to suppress subthreshold hump effect for high-voltage (HV) complementary metal-oxide-semiconductor (CMOS) technology are presented. Two methods are proposed to suppress subthreshold hump effect using a simple layout modification approach. First, the uniform gate oxide method is based on the concept of an H-shaped gate layout design. Second, the gate work function control method is accomplished by local ion implantation. For our experiments, $0.18{\mu}m$ 20 V class HV CMOS technology is applied for HV MOSFETs fabrication. From the measurements, both proposed methods are very effective for elimination of the inverse narrow width effect (INWE) as well as the subthreshold hump.

• 전기전자학회논문지
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• 제7권1호
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• pp.1-8
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• 2003

본 논문에서는 고내압 및 고속 스위칭 특성을 갖는 고성능 BCD(Bipolar- CMOS-DMOS) 소자 구조를 고안하였다. 공정 및 소자 시뮬레이션을 통하여, 최적화된 공정 규격과 소자 규격을 설계하였으며, 고안된 소자의 전기적 특성을 만족시키기 위하여 이중 매몰층 구조, 트랜치 격리 공정, n-/p- 드리프트 영역 형성기술 및 얕은 접합 깊이 형성기술 등을 채택하였다. 이 스마트 파워 IC는 20V급 Bipolar npn/pnp 소자, 60V급 LDMOS소자, 수 암페어급의 VDMOS, 20V급 CMOS소자 그리고 5V급 논리 CMOS를 내장하고 있다.