• Proceedings of the Korean Reliability Society Conference
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• 2001.06a
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• pp.239-244
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• 2001

Today, Ultrasonic is used as an important non-destructive test tool of semiconductor reliability evaluation and failure analysis. The semiconductor packaging trend goes to develop thin package, this trend makes difficult to inspect to defect in semiconductor package. One of the important problem in all semiconductor is moisture absorption in the atmosphere. This moisture causes crack or delamination to package when the semiconductor package is soldered on PCB. Reliability evaluation of semiconductor's object is investigating the effect of this moisture. For that reason, this study is investigating the effect of this moisture and reliability evaluation of semiconductor after preconditioning test and scanning acoustic microscope.

• Korean Journal of Materials Research
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• v.19 no.5
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• pp.288-292
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• 2009

This article shows various factors that influence the thermal-cycling reliability of semiconductor devices utilizing the lead-on-chip (LOC) die attach technique. This work details how the modification of LOC package design as well as the back-grinding and dicing process of semiconductor wafers affect passivation reliability. This work shows that the design of an adhesion tape rather than a plastic package body can play a more important role in determining the passivation reliability. This is due to the fact that the thermal-expansion coefficient of the tape is larger than that of the plastic package body. Present tests also indicate that the ceramic fillers embedded in the plastic package body for mechanical strengthening are not helpful for the improvement of the passivation reliability. Even though the fillers can reduce the thermal-expansion of the plastic package body, microscopic examinations show that they can cause direct damage to the passivation layer. Furthermore, experimental results also illustrate that sawing-induced chipping resulting from the separation of a semiconductor wafer into individual devices might develop into passivation cracks during thermal-cycling. Thus, the proper design of the adhesion tape and the prevention of the sawing-induced chipping should be considered to enhance the passivation reliability in the semiconductor devices using the LOC die attach technique.

• Journal of Korean Institute of Industrial Engineers
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• v.38 no.1
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• pp.46-56
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• 2012

The purpose of virtual metrology (VM) in semiconductor manufacturing is to predict every wafer's metrological values based on its process equipment data without an actual metrology. In this paper, we propose novelty detection-based reliability estimation models for VM in order to support flexible utilization of VM results. Because the proposed model can not only estimate the reliability of VM, but also identify suspicious process variables lowering the reliability, quality control actions can be taken selectively based on the reliance level and its causes. Based on the preliminary experimental results with actual semiconductor manufacturing process data, our models can successfully give a high reliance level to the wafers with small prediction errors and a low reliance level to the wafers with large prediction errors. In addition, our proposed model can give more detailed information by identifying the critical process variables and their relative impacts on the low reliability.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.3
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• pp.141-157
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• 2001

Highly reliable packaged 64kbit ferroelectric memories with $0.8{\;}\mu\textrm{m}$ CMOS ensuring ten-year retention and imprint at 125^{\circ}C$ have been successfully developed. These superior reliabilities have resulted from steady integration schemes free from the degradation, due to layer stress and attacks of process impurities. The resent results of research and development for ferroelectric memories at Hynix Semiconductor Inc. are summarized in this invited paper.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1426-1437
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• 2016

In different industrial and mission oriented applications, redundant or standby semiconductor systems can be implemented to improve the reliability of power electronics equipment. The proper structure for implementation can be one of the redundant or standby structures for series or parallel switches. This selection is determined according to the type and failure rate of the fault. In this paper, the reliability and the mean time to failure (MTTF) for each of the series and parallel configurations in two redundant and standby structures of semiconductor switches have been studied based on different failure rates. The Markov model is used for reliability and MTTF equation acquisitions. According to the different values for the reliability of the series and parallel structures during SC and OC faults, a comprehensive comparison between each of the series and parallel structures for different failure rates will be made. According to the type of fault and the structure of the switches, the reliability of the switches in the redundant structure is higher than that in the other structures. Furthermore, the performance of the proposed series and parallel structures of switches during SC and OC faults, results in an improvement in the reliability of the boost dc/dc converter. These studies aid in choosing a configuration to improve the reliability of power electronics equipment depending on the specifications of the implemented devices.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.2
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• pp.35-41
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• 2011

Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.1-7
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• 2006

A major failure mode for wafer level chip size package (WLCSP) is thermo-mechanical fatigue of solder joints. The mechanical strains and stresses generated by the coefficient of thermal expansion (CTE) mismatch between the die and printed circuit board (PCB) are usually the driving force for fatigue crack initiation and propagation to failure. In a WLCSP process peripheral or central bond pads from the die are redistributed into an area away using an insulating polymer layer and a redistribution metal layer, and the insulating polymer layer affects solder joints reliability by absorption of stresses generated by CTE mismatch. In this study, several insulating polymer materials were applied to WLCSP to investigate the effect of insulating material. It was found that the effect of property of insulating material on WLCSP reliability was altered with a solder ball layout of package.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.240-249
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• 2004

In the present paper efforts have been made to optimize InAlAs/InGaAs HEMT by enhancing the effective gate voltage ($(V_c-V_off)$) using pulsed doped structure from uniformly doped to delta doped for microwave frequency applications and reliability. The detailed design criteria to select the proper design parameters have also been discussed in detail to exclude parallel conduction without affecting the del ice performance. Then the optimized value of $V_c-V_off$and breakdown voltages corresponding to maximum value of transconductance has been obtained. These values are then used to predict the transconductance and cut-off frequency of the del ice for different channel depths and gate lengths.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.3 s.96
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• pp.25-29
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• 1999

The lead frame manufactured by press stamping process, is an important part of semiconductor. The recent technical trend of semiconductor, chip sized and high performance package technology, requires the lead frame to be of more multi-leads and of fine ILP (Inner Lead Pitch). As the ILP is getting finer, its corresponding punch of the stamping die is getting narrower. The punch narrower than its stamping limit has been broken due to local buckling. This paper analyzed the phenomena of punch breakdown. Moreover, the punch design was modified to increase the critical limit of buckling force. This paper, also, suggested new design rules of the punch, which asks the modification of its lead frame design that has to be considered in the stage of semiconductor package design. The new design rules of lead frame design yields a good reliability of semiconductor package as well as a good quality of lead frame.

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.43-48
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• 2023

This paper discusses the design of 32Mbyte asynchronous nonvolatile memory modules, which includes self-diagnosis and RTC (Real Time Clock) functions to enhance their data stability and reliability. Nonvolatile memory modules can maintain data even in a power-off state, thereby improving the stability and reliability of a system or device. However, due to the possibility of data error due to electrical or physical reasons, additional data loss prevention methods are required. To minimize data error in asynchronous nonvolatile memory modules, this paper proposes the use of voltage monitoring circuits, self-diagnosis, BBT (Bad Block Table), ECC (Error Correction Code), CRC (Cyclic Redundancy Check)32, and data check sum, data recording method using RTC. Prototypes have been produced to confirm correct operation and suggest the possibility of commercialization.