[KSCI] Korea Science Citation Index Service

http://dx.doi.org/10.6117/kmeps.2011.18.2.035

A Study on the/ Correlation Between Board Level Drop Test Experiment and Simulation

Kang, Tae-Min (PKG R&D Division, PKG Design Technology Team, Hynix Semiconductor Inc.)
Lee, Dae-Woong (PKG R&D Division, PKG Design Technology Team, Hynix Semiconductor Inc.)
Hwang, You-Kyung (PKG R&D Division, PKG Design Technology Team, Hynix Semiconductor Inc.)
Chung, Qwan-Ho (PKG R&D Division, PKG Design Technology Team, Hynix Semiconductor Inc.)
Yoo, Byun-Kwang (PKG R&D Division, PKG Design Technology Team, Hynix Semiconductor Inc.)

Publication Information

Journal of the Microelectronics and Packaging Society / v.18, no.2, 2011 , pp. 35-41 More about this Journal

Abstract

Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.

Keywords

Board level drop test; Package drop test; Drop test;

Citations & Related Records

Times Cited By KSCI : 1 (Citation Analysis)

Reference
Cited By KSCI

1	JEDEC Standard JESD22-B111, Board Level Drop Test Method of Components for Handheld Electronic Products (2003).
2	JEDEC Standard JESD22-200-BAA0, Subassembly Mechanical Shock (2001).
3	Luan, J.E., Tee, T.Y., Pek, E., Lim, C.T., and Zhong, Z.W., "Modal Analysis and Dynamic Responses of Board Level Drop Test", 5th EPTC Conference Proc., pp. 233-243, Singapore (2003).
4	Luan, J.E., Tee, T.Y., "Novel Board Level Drop Test Simulation using Implicit Transient Analysis with Input-G Method", 6th EPTC Conference Proc., Singapore (2004).
5	Luan, J.E., Tee, T.Y., "Drop Impact Simulation Using Implicit Input-G Method", 5th ANSYS Asian Conference (2005).
6	Luan, J.E., Tee, T.Y., "Simulation using Implicit Transient Analysis with Input-G Method", 6th EPTC Conference Proc., Singapore (2004).
7	T. Y. Tee, J. E. Luan, E. Pek, C. T. Lim, and Z. W. Zhong, "Novel numerical and experimental analysis of dynamic responses under board level drop test", in Proc. EuroSime Conf., Belgium (2004).
8	Chengalva, M., Jeter, N., Baxter, S.C., "Effect of Circuit Board Flexure on Flip Chips before Underfill", Proc. 50th Electronic Components and Technology Conference, Las Vegas, NV, USA (2000).
9	H. S. Ahn, J. Y. Lim and D. Y. Jang, "Experimental and Numerical Study on Board Level Impact Test of SnPb and SnAgCu BGA Assembly Packaging", J. Microelectron. Packag. Soc., 15(4), 77 (2008).
10	S. B. Jung, J. H. Park and Y. C. Chu, "Drop reliability evaluation of Sn-3.0Ag-0.5Cu solder joint with OSP and ENIG surface finishes", J. Microelectron. Packag. Soc., 16(1), 33 (2009).
11	Xie, D., Arra, M., Yi, S., and Rooney, D., "Solder Joint Behavior of Area Airray Ptkages in Board Level Drop for Handheld Devices", 53rd ECTC Conference Proc..R (2003).
12	Tee TY, Ng HS, Lim CT, Pek E, Zhong ZW, "Application of drop test simulation in electronic packaging", 4th ASEAN ANSYS Conference, Singapore (2002).
13	Tee TY, Luan JE, Pek E, Lim CT, Zhong ZW, "Advanced experimental and simulation techniques for analysis of dynamic responses during drop impact", In: Proceedings of the 54th ECTC Conference (2004).