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http://dx.doi.org/10.6117/kmeps.2011.18.2.035

A Study on the/ Correlation Between Board Level Drop Test Experiment and Simulation  

Kang, Tae-Min (PKG R&D Division, PKG Design Technology Team, Hynix Semiconductor Inc.)
Lee, Dae-Woong (PKG R&D Division, PKG Design Technology Team, Hynix Semiconductor Inc.)
Hwang, You-Kyung (PKG R&D Division, PKG Design Technology Team, Hynix Semiconductor Inc.)
Chung, Qwan-Ho (PKG R&D Division, PKG Design Technology Team, Hynix Semiconductor Inc.)
Yoo, Byun-Kwang (PKG R&D Division, PKG Design Technology Team, Hynix Semiconductor Inc.)
Publication Information
Journal of the Microelectronics and Packaging Society / v.18, no.2, 2011 , pp. 35-41 More about this Journal
Abstract
Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.
Keywords
Board level drop test; Package drop test; Drop test;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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