• Journal of the Korea Convergence Society
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• v.8 no.11
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• pp.43-48
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• 2017

Semiconductors are leading the development of industrial technology, leading to miniaturization and weight reduction of electronic products as a leading technology, we are dragging the electronic industry market Especially, the semiconductor manufacturing process is composed of highly accurate and complicated processes, and effective production is required Recently, a vision system combining a computer and a camera is utilized for defect detection In addition, the demand for a system for measuring the shape of a fine pattern processed by a special process is rapidly increasing. In this paper, we propose a vision algorithm using mask image to detect scratch defect of semiconductor pockage. When applied to the manufacturing process of semiconductor packages via the proposed system, it is expected that production management can be facilitated, and efficiency of production will be enhanced by failure judgment of high-speed packages.

• Journal of the Korean Society for Precision Engineering
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• v.27 no.6
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• pp.32-38
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• 2010

Laser material processing technology is adopted in several industry as alternative process which could overcome weakness and problems of present adopted process, especially semiconductor and display industry. In semiconductor industry, laser photo lithography is doing at front-end level, and cutting, drilling, and marking technology for both wafer and EMC mold package is adopted. Laser cleaning and de-flashing are new rising technology. There are 3 kinds of main display industry which use laser technology - TFT LCD, AMOLED, Touch screen. Laser glass cutting, laser marking, laser direct patterning, laser annealing, laser repairing, laser frit sealing are major application in display industry.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.31-35
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• 2013

TSOP(Thin Small Outline Package) is the IC package using lead frame, which is the type of low cost package for white electronics, auto mobile, desktop PC, and so on. Its performance is not excellent compared to BGA or flip-chip CSP, but it has been used mostly because of low price of TSOP package. However, it has been issued in TSOP package that thermal deflection of lead frame occurs frequently during molding process and Au wire between semiconductor die and pad is debonded. It has been required to solve this problem through substituting materials with low CTE and improving structure of lead frame. We focused on developing the lead frame structure having thermal stability, which was carried out by numerical analysis in this study. Thermal deflection of lead frame in TSOP package was simulated with positions of anti-deflection adhesives, which was ranging 198 um~366 um from semiconductor die. It was definitely understood that thermal deflection of TSOP package with anti-deflection adhesives was improved as 30.738 um in the case of inside(198 um), which was compared to that of the conventional TSOP package. This result is caused by that the anti-deflection adhesives is contributed to restrict thermal expansion of lead frame. Therefore, it is expected that the anti-deflection adhesives can be applied to lead frame packages and enhance their thermal deflection without any change of substitutive materials with low CTE.

• Journal of Korean Institute of Industrial Engineers
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• v.41 no.6
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• pp.579-587
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• 2015

Semiconductor manufacturing industry is a high density integration industry because it generates a vest number of data that takes about 300~400 processes that is supervised by numerous production parameters. It is asked of engineers to understand the correlation between different stages of the manufacturing process which is crucial in reducing production costs. With complex manufacturing processes, and defect processing time being the main cause. In the past, it was possible to grasp the corelation among manufacturing process stages through the engineer's domain knowledge. However, It is impossible to understand the corelation among manufacturing processes nowadays due to high density integration in current semiconductor manufacturing. in this paper we propose a canonical correlation analysis (CCA) using both wafer test voltage variables and fail bit counts variables. using the method we suggested, we can increase the semiconductor yield which is the result of the package test.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.53-58
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• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)

• Composites Research
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• v.34 no.1
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• pp.47-50
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• 2021

In this paper, the Curing process for Epoxy Molding Compound (EMC) Package was developed by comparing the performance of the EMC/Cu Bi-layer package manufactured by the conventional Hot Press process system and Carbon Nanotubes (CNT) Heater process system of the surface heating system. The viscosity of EMC was measured by using a rheometer for the curing cycle of the CNT Heater. In the EMC/Cu Bi-layer Package manufactured through the two process methods by mentioned above, the voids inside the EMC was analyzed using an optical microscope. In addition, the interfacial void and warpage of the EMC/Cu Bi-layer Package were analyzed through C-Scanning Acoustic Microscope and 3D-Digital Image Correlation. According to these experimental results, it was confirmed that there was neither void in the EMC interior nor difference in the warpage at room temperature, the zero-warpage temperature and the change in warpage.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.4
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• pp.83-87
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• 2022

Recently, as the thickness of the semiconductor package becomes thinner, warpage has become a major issue. Since the warpage is caused by differences in material properties between package components, it is essential to precisely evaluate the material properties of the EMC(Epoxy molding compound), one of the main components, to predict the warpage accurately. Especially, the cure shrinkage of the EMC is generated during the curing process, and among them, the effective cure shrinkage that occurs after the gelation point is a key factor in warpage. In this study, the gelation point of the EMC was defined from the dissipation factor measured using the dielectric sensor during the curing process similar with actual semiconductor package. In addition, DSC (Differential scanning calorimetry) test and rheometer test were conducted to analyze the dielectrometry measurement. As a result, the dielectrometry was verified to be an effective method for monitoring the curing status of the EMC. Simultaneously, the strain transition of the EMC during the curing process was measured using the FBG (Fiber Bragg grating) sensor. From these results, the effective cure shrinkage of the EMC during the curing process was measured.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.3-6
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• 2004

Power semiconductor devices are being compact, high performance and intelligent thanks to recent remarkable developments of silicon design, process and related packaging technologies. Developments of MOS-gate transistors such as MOSFET and IGBT are dominant thanks to their advantages on high speed operation. In conjunction with package technology, silicon technologies such as trench, charge balance and NPT will support future power semiconductors. In addition, wide band gap material such as SiC and GaN are being studies for next generation power semiconductor devices.

• Journal of the Korean institute of surface engineering
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• v.8 no.2
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• pp.1-6
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• 1975

A novel electroplating process is described and effects of anode lay-out thickness distribution and on platiting rate are discussed. Microphotograhic analysis indicates are compact and less "POROUS " than of barrel and rack. With this process production cost reduction and capacity increase could be achieved by a rate of 60% and 97% respectively, as compared to our present barrel plating process. This process disclose a number of beneficial processes such as color coding system on TO-92 package and development of a new tin bath formula.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.139-149
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• 2012

A 3D stacked IC is made by multiple dies (possibly) with heterogeneous process technologies. Therefore, die-to-die variation in 2D chips renders on-package variation (OPV) in a 3D chip. In spite of the different variation effect in 3D chips, generally, 3D die stacking can produce high yield due to the smaller individual die area and the averaging effect of variation on data path. However, 3D clock network can experience unintended huge clock skew due to the different clock propagation routes on multiple stacked dies. In this paper, we analyze the on-package variation effect on 3D clock networks and show the necessity of a post silicon management method such as body biasing technique for the OPV induced 3D clock skew control in 3D stacked IC designs. Then, we present a parametric yield improvement method to mitigate the OPV induced 3D clock skew.