• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.98.4-98
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• 1998

• Journal of the Semiconductor & Display Technology
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• v.2 no.2
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• pp.21-24
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• 2003

Seam seal welding on the semiconductor package is a process for sealing the packages of semi-conductors, crystal parts, saw filters and oscillators with lid plate by seam welding. This paper presents the development process of automatic seam seal welding system. In this process, the process algorithm, high precision welding current control, design of welding head, high speed and high precision feeding mechanism and user interface process control program technologies are included.

• Korean Journal of Computational Design and Engineering
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• v.19 no.4
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• pp.402-409
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• 2014

Presented in this paper is a scheduling method for semiconductor backend process considering the backward pegging. It is known that the pegging for frontend is a process of labeling WIP lots for target order which is specified by due date, quantity, and product specifications including customer information. As a result, it gives the release plan to meet the out target considering current WIP. However, the semiconductor backend process includes the multichip package and test operation for the product bin portion. Therefore, backward pegging method for frontend can't give the release plan for backend process in semiconductor. In this paper, we suggest backward pegging method considering the characteristics of multichip package and test operation in backend process. And we describe the backward pegging problem using the examples.

• Korean Journal of Materials Research
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• v.19 no.5
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• pp.288-292
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• 2009

This article shows various factors that influence the thermal-cycling reliability of semiconductor devices utilizing the lead-on-chip (LOC) die attach technique. This work details how the modification of LOC package design as well as the back-grinding and dicing process of semiconductor wafers affect passivation reliability. This work shows that the design of an adhesion tape rather than a plastic package body can play a more important role in determining the passivation reliability. This is due to the fact that the thermal-expansion coefficient of the tape is larger than that of the plastic package body. Present tests also indicate that the ceramic fillers embedded in the plastic package body for mechanical strengthening are not helpful for the improvement of the passivation reliability. Even though the fillers can reduce the thermal-expansion of the plastic package body, microscopic examinations show that they can cause direct damage to the passivation layer. Furthermore, experimental results also illustrate that sawing-induced chipping resulting from the separation of a semiconductor wafer into individual devices might develop into passivation cracks during thermal-cycling. Thus, the proper design of the adhesion tape and the prevention of the sawing-induced chipping should be considered to enhance the passivation reliability in the semiconductor devices using the LOC die attach technique.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.05a
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• pp.34-39
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• 2003

Seam seal welding on the semi-conductor package is a process for sealing the packages of semiconductors, crystal parts, saw filters, oscillators with lid plate by seam welding. This paper present the development process of automatic seam seal welding system. In this process, the process algorithm, high precision welding current control, design of welding head, high speed and high precision feeding mechanism, user interface process control program technologies are included.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.3 s.96
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• pp.25-29
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• 1999

The lead frame manufactured by press stamping process, is an important part of semiconductor. The recent technical trend of semiconductor, chip sized and high performance package technology, requires the lead frame to be of more multi-leads and of fine ILP (Inner Lead Pitch). As the ILP is getting finer, its corresponding punch of the stamping die is getting narrower. The punch narrower than its stamping limit has been broken due to local buckling. This paper analyzed the phenomena of punch breakdown. Moreover, the punch design was modified to increase the critical limit of buckling force. This paper, also, suggested new design rules of the punch, which asks the modification of its lead frame design that has to be considered in the stage of semiconductor package design. The new design rules of lead frame design yields a good reliability of semiconductor package as well as a good quality of lead frame.

• Journal of the Semiconductor & Display Technology
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• v.21 no.1
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• pp.148-154
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• 2022

As the 4th industrial age approaches, the demand for semiconductors is increasing enough to be used in all electronic devices. At the same time, semiconductor technology is also developing day by day, leading to ultraprecision and low power consumption. Semiconductors that keep getting smaller generate heat because the energy density increases, and the generated heat changes the shape of the semiconductor package, so it is important to manage. The temperature change is not only self-heating of the semiconductor package, but also heat generated by external damage. If the package is deformed, it is necessary to manage it because functional problems and performance degradation such as damage occur. The package burn in test in the post-process of semiconductor production is a process that tests the durability and function of the package in a high-temperature environment, and heat dissipation performance can be evaluated. In this paper, we intend to review a new material formulation that can improve the performance of the adapter, which is one of the parts of the test socket used in the burn-in test. It was confirmed what characteristics the basic base showed when polyamide, a high-molecular material, and alumina, which had high thermal conductivity, were mixed for each magnification. In this study, functional evaluation was also carried out by injecting an adapter, a part of the test socket, at the same time as the specimen was manufactured. Verification of stiffness such as tensile strength and flexural strength by mixing ratio, performance evaluation such as thermal conductivity, and manufacturing of a dummy device also confirmed warpage. As a result, it was confirmed that the thermal stability was excellent. Through this study, it is thought that it can be used as basic data for the development of materials for burn-in sockets in the future.

• Journal of Korean Institute of Industrial Engineers
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• v.41 no.3
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• pp.267-274
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• 2015

In the semiconductor manufacturing post-FAB process, predicting a package test result accurately in the wafer testing phase is a key element to ensure the competitiveness of companies. The prediction of package test can reduce unnecessary inspection time and expense. However, an analysing method is not sufficient to analyze data collected at wafer testing phase. Therefore, many companies have been using a summary information such as a mean, weighted sum and variance, and the summarized data reduces a prediction accuracy. In the paper, we propose an analysis method for Wafer Map Image collected at wafer testing process and conduct an experiment using real data.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.216-231
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• 2001

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.17 no.3
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• pp.14-19
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• 2008

In the semiconductor IC(Integrated Circuit) package, the top surface of silicon chip is directly attached to the area of the leadframe with a double-sided adhesive layer, in which the base layer have the upper adhesive layer and the lower adhesive layer. The IC package structure has been known to encounter a thermo-mechanical failure mode such as delamination. This failure mode is due to the residual stress on the adhesive surface of silicon chip and leadframe in the curing-cooling process. The induced thermal stress in the curing process has an influence on the cooling residual stress on the silicon chip and leadframe. In this paper, for the minimization of the chip surface damage, the adhesive topologies on the silicon chip are studied through the finite element analysis(FEA).