• 한국자기학회:학술대회 개요집
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• 한국자기학회 2007년도 The 1st International Symposium on Advanced Magnetic Materials
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• pp.179.1-179.1
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• 2007

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2008년도 하계학술연구발표회
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• pp.112-113
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• 2008

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2007년도 The 1st International Symposium on Advanced Magnetic Materials
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• pp.202.2-202.2
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• 2007

• 산업공학
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• 제16권spc호
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• pp.93-98
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• 2003

This paper addresses an AGV dispatching problem in semiconductor clean-room bays where AGVs move cassettes of wafers between machines or machines and a central buffer. Since each machine in a bay has a local buffer of limited capacity, material flow should be controlled in a careful way to maintain high system performance. It is regarded that two most important performance measures in a semiconductor bay are throughput rate and lead-time. The throughput rate is determined by a bottleneck resource and the lead-time depends on smooth material flow in the system. This paper presents an AGV dispatching procedure based on the concept of theory of constraints (TOC), by which dispatching decisions are made to utilize the bottleneck resource at the maximum level and to smooth the flow of material. The new dispatching procedure is compared with existing dispatching rules through simulation experiments.

• Transactions on Electrical and Electronic Materials
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• 제5권6호
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• pp.219-222
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• 2004

This paper discovers that there are some peculiar properties that can remove holography grating, which was made in chacogenide thin film by impressed voltage. The thin films were used are $As_{40}Ge_{10}Se_{15}S_{35}$, and we use He-Ne laser in order to form thin films. I-V curved line in a thin film before a lattice was made has the critical point, about 3.7 V. Moreover, the I-V curved line increased current intensity at over 4 V after it made thin film. In addition, while holography grating is being made, and when it has the highest diffraction efficiency, a lattice can be deleted if put more voltage into it.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권2호
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• pp.69-75
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• 2003

Cell transistor and data retention time characteristics were studied in 90 nm design rule 512M-bit DRAM, for the first time. And, the characteristics of cell transistor are investigated for different STI gap-fill materials. HDP oxide with high compressive stress increases the threshold voltage of cell transistor, whereas the P-SOG oxide with small stress decreases the threshold voltage of cell transistor. Stress between silicon and gap-fill oxide material is found to be the major cause of the shift of the cell transistor threshold voltage. If high stress material is used for STI gap fill, channel-doping concentration can be reduced, so that cell junction leakage current is decreased and data retention time is increased.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.192-193
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• 2006

The wet coating process could easily be made from large area film with printing paste mixed with semiconductor and binder material at room temperature. Semiconductor film fabricated about 25mm thickness was evaluated by field emissions-canning electron microscopy (FE-SEM). X-ray performance data such as dark current, sensitivity and signal to noise ratio (SNR) were evaluated. The $Hgl_2$ semiconductor was shown in much lower dark current than the others, but the best sensitivity. In this paper, reactivity and combination character of semiconductor and binder material that affect electrical and X-ray detection properties would prove out though experimental results.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.3-6
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• 2004

반도체 디자인, 공정 기술 및 패기지 기술의 발달에 따라 전력용 반도체는 소형화, 고성능화, 지능화하고 있다. 고속 구동이 용이한 때문에 MOSFET이나 IGBT등의 MOS-gate형 전력 반도체의 발전이 두드려지며, trench, charge balance, NPT 기술등이 패키지 기술과 더불어 이를 위한 주요 기술이 될것으로 보인다. SiC나 GaN등의 Wide Band Gap 물질들을 사용한 차세대 전력 반도체 연구도 활발히 진행되고 있다.

• 한국전기전자재료학회논문지
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• 제13권3호
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• pp.200-205
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• 2000

This paper describes the structure modeling and operation characteristics of MFMIS(metal-ferroelectric-metal-insulator-semiconductor) device using the Tsuprem4 which is a semiconductor device tool by Avanti. MFMIS device is being studied for nonvolatile memory application at various semiconductor laboratory but it is difficult to fabricate and analyze MFMIS devices using the semiconductor simulation tool: Tsuprem4, medici and etc. So the new library and new materials parameters for adjusting ferroelectric material and platinum electrodes in the tools are studied. In this paper structural model and operation characteristics of MFMIS devices are measured, which can be easily adopted to analysis of MFMIS device for nonvolatile memory device application.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권2호
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• pp.76-82
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• 2003

The robust stack storage node and sufficient cell capacitance for high performance is indispensable for 90 nm DRAM capacitor. For the first time, we successfully demonstrated MIS capacitor process integration for 90 nm DRAM technology. Novel cell layout and integration technology of 90 nm DRAM capacitor is proposed and developed, and it can be extended to the next generation DRAM. Diamond-shaped OCS with 1.8 um stack height is newly developed for large capacitor area with better stability. Furthermore, the novel $Al_2O_3/HfO_2$ dielectric material with equivalent oxide thickness (EOT) of 25 ${\AA}$ is adopted for obtaining sufficient cell capacitance. The reliable cell capacitance and leakage current of MIS capacitor is obtained with ~26 fF/cell and < 1 fA/ceil by $Al_2O_3/HfO_2$ dielectric material, respectively.