• Title/Summary/Keyword: Semiconductor layer

Search Result 1,404, Processing Time 0.029 seconds

Theoretical Calculation and Experimental Verification of the Hf/Al Concentration Ratio in Nano-mixed $Hf_xAl_yO_z$ Films Prepared by Atomic Layer Deposition

  • Kil, Deok-Sin;Yeom, Seung-Jin;Hong, Kwon;Roh, Jae-Sung;Sohn, Hyun-Cheol;Kim, Jin-Woong;Park, Sung-Wook
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.5 no.2
    • /
    • pp.120-126
    • /
    • 2005
  • We have proposed a characteristic method to estimate real composition when multi component oxide films are deposited by ALD. Final atomic concentration ratio was theoretically calculated from the film densities and growth rates for $HfO_2$ and $Al_2O_3$ using ALD processed HfxAhOz mms.W e have transformed initial source feeding ratio during deposition to fins] atomic ratio in $Hf_xAl_yO_z$ films through thickness factors ($R_{HFO_2}$ ami $R_{Al_2O_3}$) ami concentration factor(C) defined in our experiments. Initial source feeding ratio could be transformed into the thickness ratio by each thickness factor. Final atomic ratio was calculated from thickness ratio by concentration factor. It has been successfully confirmed that the predicted atomic ratio was in good agreement with the actual measured value by ICP-MS analysis.

Study of Plasma Process Induced Damages on Metal Oxides as Buffer Layer for Inverted Top Emission Organic Light Emitting Diodes

  • Kim, Joo-Hyung;Lee, You-Jong;Jang, Jin-Nyoung;Song, Byoung-Chul;Hong, Mun-Pyo
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • 2008.10a
    • /
    • pp.543-544
    • /
    • 2008
  • In the fabrication of inverted top emission organic light emitting diodes (ITOLEDs), the organic layers are damaged by high-energy plasma sputtering process for transparent top anode. In this study, the plasma process induced damages on metal oxide hole injection layers (HILs) including $WO_3$, $MoO_3$, and $V_2O_5$ as buffer layer are examined. With the result of IV characteristic of hole-only devices, we propose that $MoO_3$ and $V_2O_5$ are stable materials against plasma sputtering process.

  • PDF

Pentacene OTFTs with $Al_2O_3$ gate insulator by Atomic Layer Deposition Process

  • Jin, Sung-Hun;Kim, Jin-Wook;Lee, Cheon-An;Park, Byung-Gook;Lee, Jong-Duk
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • 2003.07a
    • /
    • pp.15-18
    • /
    • 2003
  • Pentacene OTFTs of $Al_2O_3$ insulator treated with a diluted PMMA were fabricated for the application of the low voltage operation and large area displays. The operation voltage of 15 V and the mobility of 0.35 $cm^2/Vsec$ are obtained even adopting the thick dielectric of 100 nm which was deposited by atomic layer deposition at the temperature of $150^{\circ}C$. The current on-off ratio was $4.1{\times}10^4$ for the OTFTs treated with 9:1 PMMA and good saturation characteristics were obtained as drain voltage increases.

  • PDF

Plasma Treatment Effects on Tungsten Oxide Hole Injection Layer for Application to Inverted Top-Emitting Organic Light-Emitting Diodes

  • Kim, Joo-Hyung;Lee, You-Jong;Jang, Yun-Sung;Kim, Doo-Hyun;Hong, Mun-Pyo
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • 2009.10a
    • /
    • pp.354-355
    • /
    • 2009
  • In the fabrication of inverted top-emitting organic light emitting diodes (ITOLEDs), the sputtering process is needed for deposition of transparent conducting oxide (TCO) as top anode. Energetic particle bombardment, however, changes the physical properties of underlying layers. In this study, we examined plasma process effects on tungsten oxide ($WO_3$) hole injection layer (HIL). From our results, we suggest the theoretical mechanism to explain the correlation between the physical property changes caused by plasma process on $WO_3$ HIL and degradation of device performances.

  • PDF

Memristive Devices Based on RGO Nano-sheet Nanocomposites with an Embedded GQD Layer (저결함 그래핀 양자점 구조를 갖는 RGO 나노 복합체 기반의 저항성 메모리 특성)

  • Kim, Yongwoo;Hwang, Sung Won
    • Journal of the Semiconductor & Display Technology
    • /
    • v.20 no.1
    • /
    • pp.54-58
    • /
    • 2021
  • The RGO with controllable oxygen functional groups is a novel material as the active layer of resistive switching memory through a reduction process. We designed a nanoscale conductive channel induced by local oxygen ion diffusion in an Au / RGO+GQD / Al resistive switching memory structure. A strong electric field was locally generated around the Al metal channel generated in BIL, and the local formation of a direct conductive low-dimensional channel in the complex RGO graphene quantum dot region was confirmed. The resistive memory design of the complex RGO graphene quantum dot structure can be applied as an effective structure for charge transport, and it has been shown that the resistive switching mechanism based on the movement of oxygen and metal ions is a fundamental alternative to understanding and application of next-generation intelligent semiconductor systems.

Pd Seed Layer for Electroless Cu Deposition on TaN Diffusion Barrier by Self-Assembled-Monolayer Method(SAM) (Self assembled-monolayer(SAM)법을 이용한 TaN 확산방지막의 무전해 Cu 도금용 Pd seed layer 제조 및 특성)

  • Han, Won-Kyu;Cho, Jin-Ki;Choi, Jae-Woong;Kim, Jeong-Tae;Yeom, Seung-Jin;Kwak, Noh-Jung;Kim, Jin-Woong;Kang, Sung-Goon
    • Korean Journal of Materials Research
    • /
    • v.17 no.9
    • /
    • pp.469-474
    • /
    • 2007
  • Electroless deposition(ELD) was applied to fabricate Cu interconnections on a TaN diffusion barrier with Pd seed layer. The Pd seed layer was obtained by self-assembled monolayer method(SAM) with PDDA and PSS as surfactants. We were able to obtain about 10nm Pd nano particles as seeds for electroless Cu deposition and the density of Pd seeds was much higher than that of Pd seeds fabricated by conventional Pd sensitization-activation method. Also we were able to obtain finer Cu interconnections by ELD. Therefore we concluded that the Pd seed layer by SAM was able to be applied to form Cu interconnection by ELD for under 30nm feature.

Improvement in Capacitor Characteristics of Titanium Dioxide Film with Surface Plasma Treatment (플라즈마 표면 처리를 이용한 TiO2 MOS 커패시터의 특성 개선)

  • Shin, Donghyuk;Cho, Hyelim;Park, Seran;Oh, Hoonjung;Ko, Dae-Hong
    • Journal of the Semiconductor & Display Technology
    • /
    • v.18 no.1
    • /
    • pp.32-37
    • /
    • 2019
  • Titanium dioxide ($TiO_2$) is a promising dielectric material in the semiconductor industry for its high dielectric constant. However, for utilization on Si substrate, $TiO_2$ film meets with a difficulty due to the large leakage currents caused by its small conduction band energy offset from Si substrate. In this study, we propose an in-situ plasma oxidation process in plasma-enhanced atomic layer deposition (PE-ALD) system to form an oxide barrier layer which can reduce the leakage currents from Si substrate to $TiO_2$ film. $TiO_2$ film depositions were followed by the plasma oxidation process using tetrakis(dimethylamino)titanium (TDMAT) as a Ti precursor. In our result, $SiO_2$ layer was successfully introduced by the plasma oxidation process and was used as a barrier layer between the Si substrate and $TiO_2$ film. Metal-oxide-semiconductor ($TiN/TiO_2/P-type$ Si substrate) capacitor with plasma oxidation barrier layer showed improved C-V and I-V characteristics compared to that without the plasma oxidation barrier layer.

Simulation of Junction Field Effect Transistor using SiGe-Si-SiGe Channel Structure (SiGe-Si-SiGe 채널구조를 이용한 JFET 시뮬레이션)

  • Park, B.G.;Yang, H.Y.;Kim, T.S.;Shim, K.H.
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2008.11a
    • /
    • pp.94-94
    • /
    • 2008
  • We have performed simulation for Junction Field Effect Transistor(JFET) using Silvco to improve its electrical properties. The device structure and process conditions of Si-control JFET(Si-JFET) were determined to set its cut off voltage and drain current(at Vg=0V) to -0.5V and $300{\mu}A$, respectively. From electrical property obtained at various implantation energy, dose, and drive-in conditions of p-gate doping, we found that the drive in time of p-type gate was the most determinant factor due to severe diffusion. Therefore we newly designed SiGe-JFET, in which SiGe layer is to epitaxial layers placed above and underneath of the Si-channel. The presence of SiGe layer lessen the p-type dopants (Boron) into the n-type Si channel the phenomenon would be able to enhance the structural consistency of p-n-p junction. The influence of SiGe layer will be discussed in conjunction with boron diffusion and corresponding I-V characteristics in comparison with Si-control JFET.

  • PDF

Fabrication of Scattering Layer for Light Extraction Efficiency of OLEDs (RIE 공정을 이용한 유기발광다이오드의 광 산란층 제작)

  • Bae, Eun Jeong;Jang, Eun Bi;Choi, Geun Su;Seo, Ga Eun;Jang, Seung Mi;Park, Young Wook
    • Journal of the Semiconductor & Display Technology
    • /
    • v.21 no.1
    • /
    • pp.95-102
    • /
    • 2022
  • Since the organic light-emitting diodes (OLEDs) have been widely investigated as next-generation displays, it has been successfully commercialized as a flexible and rollable display. However, there is still wide room and demand to improve the device characteristics such as power efficiency and lifetime. To solve this issue, there has been a wide research effort, and among them, the internal and the external light extraction techniques have been attracted in this research field by its fascinating characteristic of material independence. In this study, a micro-nano composite structured external light extraction layer was demonstrated. A reactive ion etching (RIE) process was performed on the surfaces of hexagonally packed hemisphere micro-lens array (MLA) and randomly distributed sphere diffusing films to form micro-nano composite structures. Random nanostructures of different sizes were fabricated by controlling the processing time of the O2 / CHF3 plasma. The fabricated device using a micro-nano composite external light extraction layer showed 1.38X improved external quantum efficiency compared to the reference device. The results prove that the external light extraction efficiency is improved by applying the micro-nano composite structure on conventional MLA fabricated through a simple process.

Current Characteristics at p-GaP Semiconductor Interfaces (p형 GaP 반도체 계면의 전류 특성)

  • 김은익;천장호
    • Journal of the Korean Institute of Telematics and Electronics
    • /
    • v.26 no.9
    • /
    • pp.1369-1374
    • /
    • 1989
  • Electrical characteristics at the p-GaP semiconductor/CsNO3 electrolyte interfaces were investigated. It is found that such interfacial phenomena are well analyzed by semiconductor-semiconductor pn junction diode models and image charge effects of semiconductor-vacuum interfaces. The formation processes of electrical double layers and their potential variations are verified using cyclic voltammetric methods. The interfacial current are influenced by Cs+ ion coverage onto the semiconductor electrode surface and structure of electrical double layer.

  • PDF