• Title/Summary/Keyword: Semiconductor layer

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Oxidation resistnace of TaSiN diffusion barrier layers for Semiconductor memory device application (반도체 메모리 소자 응용을 위한 TaSiN 확산 방지층의 산화 저항성)

  • Shin, Woong-Chul;Lee, Eung-Min;Choi, Young-Sim;Choi, Kyu-Jeong;Choi, Eun-Suck;Jeon, Young-Ah;Park, Jong-Bong;Yoon, Soon-Gil
    • Korean Journal of Materials Research
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    • v.10 no.11
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    • pp.749-764
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    • 2000
  • Amorphous TaSiN thin films of about 90 nm thick were deposited onto poly-Si and $SiO_2/Si$ substrates by rf magnetron sputtering method. TaSiN films exhibited amorphous phase with no crystllization up to $900^{\circ}C$ in oxygen ambient. The penetration depth of oxygen diffusion increased with increasing annealing temperature in oxygen ambient and reached 20 nm deep in a $Ta_{23}Si_{29}N_{48}$ layer at $600^{\circ}C$ for 30min. The resistivity of as-deposited $Ta_{23}Si_{29}N_{48}$ thin films was about $1,300{\mu}{\Omega}-cm$, however those of annealed films markedly increased above $700^{\circ}C$ in oxygen ambient as the annealing temperature increased.

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Heterogeneous Device Packaging Technology for the Internet of Things Applications (IoT 적용을 위한 다종 소자 전자패키징 기술)

  • Kim, Sarah Eunkyung
    • Journal of the Microelectronics and Packaging Society
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    • v.23 no.3
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    • pp.1-6
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    • 2016
  • The Internet of Things (IoT) is a new technology paradigm demanding one packaged system of various semiconductor and MEMS devices. Therefore, the development of electronic packaging technology with very high connectivity is essential for successful IoT applications. This paper discusses both fan-out wafer level packaging (FOWLP) and 3D stacking technologies to achieve the integrattion of heterogeneous devices for IoT. FOWLP has great advantages of high I/O density, high integration, and design flexibility, but ultra-fine pitch redistribution layer (RDL) and molding processes still remain as main challenges to resolve. 3D stacking is an emerging technology solving conventional packaging limits such as size, performance, cost, and scalability. Among various 3D stacking sequences wafer level via after bonding method will provide the highest connectivity with low cost. In addition substrates with ultra-thin thickness, ultra-fine pitch line/space, and low cost are required to improve system performance. The key substrate technologies are embedded trace, passive, and active substrates or ultra-thin coreless substrates.

Relationship between Electrical Characteristics and Oxygen Vacancy in Accordance with Annealing Temperature of TiO2 Thin Film (TiO2 박막의 온도에 따른 산소공공의 분포와 전기적인 특성사이의 상관성)

  • Oh, Teresa
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.22 no.4
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    • pp.664-669
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    • 2018
  • To observe the relationship between the oxygen vacancy and electrical characteristics of $TiO_2$ due to the $CO_2$ gases, the $TiO_2$ were deposited by the mixing gases of $Ar:O_2=20$ sccm:20 sccm and annealed with various temperatures. The bonding structure was changed with the annealing temperature from amorphous to crystal structure, and the oxygen vacancy was also changed with these bonding structures. The $CO_2$ gas reaction of $TiO_2$ films showed the variation in accordance with the bonding structure. The capacitance increased at the amorphous structure $TiO_2$, and the current also increased. However the oxygen vacancy decreased at this amorphous structure $TiO_2$. Because of the formation of oxygen vacancies is in inverse proportion to the amorphous structure. Moreover, the diffusion current in the depletion layer such as the amorphous structure showed the difference in accordance with the $CO_2$ gas flow rates.

Endpoint Detection Using Hybrid Algorithm of PLS and SVM (PLS와 SVM복합 알고리즘을 이용한 식각 종료점 검출)

  • Lee, Yun-Keun;Han, Yi-Seul;Hong, Sang-Jeen;Han, Seung-Soo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.24 no.9
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    • pp.701-709
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    • 2011
  • In semiconductor wafer fabrication, etching is one of the most critical processes, by which a material layer is selectively removed. Because of difficulty to correct a mistake caused by over etching, it is critical that etch should be performed correctly. This paper proposes a new approach for etch endpoint detection of small open area wafers. The traditional endpoint detection technique uses a few manually selected wavelengths, which are adequate for large open areas. As the integrated circuit devices continue to shrink in geometry and increase in device density, detecting the endpoint for small open areas presents a serious challenge to process engineers. In this work, a high-resolution optical emission spectroscopy (OES) sensor is used to provide the necessary sensitivity for detecting subtle endpoint signal. Partial Least Squares (PLS) method is used to analyze the OES data which reduces dimension of the data and increases gap between classes. Support Vector Machine (SVM) is employed to detect endpoint using the data after PLS. SVM classifies normal etching state and after endpoint state. Two data sets from OES are used in training PLS and SVM. The other data sets are used to test the performance of the model. The results show that the trained PLS and SVM hybrid algorithm model detects endpoint accurately.

MoO3/p-Si Heterojunction for Infrared Photodetector (MoO3 기반 실리콘 이종접합 IR 영역 광검출기 개발)

  • Park, Wang-Hee;Kim, Joondong;Choi, In-Hyuk
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.30 no.8
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    • pp.525-529
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    • 2017
  • Molybdenum oxide ($MoO_3$) offers pivotal advantages for high optical transparency and low light reflection. Considering device fabrication, n-type $MoO_3$ semiconductor can spontaneously establish a junction with p-type Si. Since the energy bandgap of Si is 1.12 eV, a maximum photon wavelength of around 1,100 nm is required to initiate effective photoelectric reaction. However, the utilization of infrared photons is very limited for Si photonics. Hence, to enhance the Si photoelectric devices, we applied the wide energy bandgap $MoO_3$ (3.7 eV) top-layer onto Si. Using a large-scale production method, a wafer-scale $MoO_3$ device was fabricated with a highly crystalline structure. The $MoO_3/p-Si$ heterojunction device provides distinct photoresponses for long wavelength photons at 900 nm and 1,100 nm with extremely fast response times: rise time of 65.69 ms and fall time of 71.82 ms. We demonstrate the high-performing $MoO_3/p-Si$ infrared photodetector and provide a design scheme for the extension of Si for the utilization of long-wavelength light.

Investigation of InAs/InGaAs/InP Heterojunction Tunneling Field-Effect Transistors

  • Eun, Hye Rim;Woo, Sung Yun;Lee, Hwan Gi;Yoon, Young Jun;Seo, Jae Hwa;Lee, Jung-Hee;Kim, Jungjoon;Kang, In Man
    • Journal of Electrical Engineering and Technology
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    • v.9 no.5
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    • pp.1654-1659
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    • 2014
  • Tunneling field-effect transistors (TFETs) are very applicable to low standby-power application by their virtues of low off-current ($I_{off}$) and small subthreshold swing (S). However, low on-current ($I_{on}$) of silicon-based TFETs has been pointed out as a drawback. To improve $I_{on}$ of TFET, a gate-all-around (GAA) TFET based on III-V compound semiconductor with InAs/InGaAs/InP multiple-heterojunction structure is proposed and investigated. Its performances have been evaluated with the gallium (Ga) composition (x) for $In_{1-x}Ga_xAs$ in the channel region. According to the simulation results for $I_{on}$, $I_{off}$, S, and on/off current ratio ($I_{on}/I_{off}$), the device adopting $In_{0.53}Ga_{0.47}As$ channel showed the optimum direct-current (DC) performance, as a result of controlling the Ga fraction. By introducing an n-type InGaAs thin layer near the source end, improved DC characteristics and radio-frequency (RF) performances were obtained due to boosted band-to-band (BTB) tunneling efficiency.

Study on the Buried Semiconductor in Organic Substrate (SoP-L 기술 기반의 반도체 기판 함몰 공정에 관한 연구)

  • Lee, Gwang-Hoon;Park, Se-Hoon;Yoo, Chan-Sei;Lee, Woo-Sung;Kim, Jun-Chul;Kang, Nam-Kee;Yook, Jong-Gwan;Park, Jong-Chul
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2007.06a
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    • pp.33-33
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    • 2007
  • SoP-L 공정은 유전율이 상이한 재료를 이용하여 PCB 공정이 가능하고 다른 packaging 방법에 비해 공정 시간과 비용이 절약되는 잠정이 있다. 본 연구에서는 SoP-L 기술을 이용하여 Si 기판의 함몰에 판한 공정의 안정도와 함몰 시 제작된 때턴의 특성의 변화에 대해 관찰 하였다. Si 기판의 함몰에 Active device를 이용하여 특성의 변화를 살펴보고 공정의 안정도를 확립하려 했지만 Active device는 측정 시 bias의 확보와 특성의 민감한 변화로 인해 비교적 측정이 용이하고 공정의 test 지표를 삼기 위해 passive device 를 구현하여 함몰해 보았다. Passive device 의 제작 과정은 Si 기판 위에 spin coating을 통해 PI(Poly Imide)를 10um로 적층한 후에 Cr과 Au를 seed layer로 증착을 하였다. 그리고 photo lithography 공정을 통하여 photo resister patterning 후에 전해 Cu 도금을 거쳐 CPW 구조로 $50{\Omega}$ line 과 inductor를 형성하였다. 제작 된 passive device의 함몰 전 특성 추출 data와 SoP-L공정을 통한 함몰 후 추출 data 비교를 통해 특성의 변화와 공정의 안정도를 확립하였다. 차후 안정된 SoP-L 공정을 이용하여 Active device를 함몰 한다면 특성의 변화 없이 size 룰 줄이는 효과와 외부 자극에 신뢰도가 강한 기판이 제작 될 것으로 예상된다.

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Analysis of a transmission line on Si-based lossy structure using Finite-Difference Time-Domain(FDTD) method (손실있는 실리콘 반도체위에 제작된 전송선로의 유한차분법을 이용한 해석)

  • 김윤석
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.9B
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    • pp.1527-1533
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    • 2000
  • Basically, a general characterization procedure based on the extraction of the characteristic impedance and propagation constant for analyzing a single MIS(Metal-Insulator-Semiconductor) transmission line is used. In this paper, an analysis for a new substrate shielding MIS structure consisting of grounded cross-bars at the interface between Si and SiO2 layer using the Finite-Difference Time-Domain (FDTD) method is presented. In order to reduce the substrate effects on the transmission line characteristics, a shielding structure consisting of grounded cross bar lines over time-domain signal has been examined. The extracted distributed frequency-dependent transmission line parameters and corresponding equivalent circuit parameters as well as quality factor have been examined as functions of cross-bar spacing and frequency. It is shown that the quality factor of the transmission line can be improved without significant change in the characteristic impedance and effectve dielectric constant.

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Characterization studies of digital x-ray detector based on mercuric iodide (Mercuric iodide 기반의 디지털 X-선 검출기의 특성 연구)

  • Cho, Sung-Ho;Park, Ji-Koon;Choi, Jang-Yong;Suck, Dae-Woo;Cha, Byung-Yul;Nam, Sang-Hee;Lee, Byum-Jong
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.11a
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    • pp.392-395
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    • 2003
  • For the purpose of digital x-ray imaging, many materials such as $PbI_2$, $HgI_2$, TlBr, CdTe and CdZnTe have been under development for servaral years as direct converter layer. $Hgl_2$ film detector have recently been shown as one of the most promising semiconductor materials to be used as direct converters in x-ray digital radiography. This paper, the $HgI_2$ films are deposited on conductive-coated glass by screen printing, in which $HgI_2$ powder is embedded in a binder and solvent, and the slurry is used to coat the conductive-coated glass. We investigated electrical characteristic of the fabricated $HgI_2$ films. The x-ray response to radiological x-ray generator of 70Kvp using the current integration mode will be reported for screen printing films. These results indicate that $HgI_2$ detectors have high potential as new digital x-ray imaging devices for radiography.

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Non-volatile Molecular Memory using Nano-interfaced Organic Molecules in the Organic Field Effect Transistor

  • Lee, Hyo-Young
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.02a
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    • pp.31-32
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    • 2010
  • In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]

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