• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.921-926
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• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.

• 제어로봇시스템학회:학술대회논문집
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• 1995.10a
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• pp.87-90
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• 1995

When the ultrasonic transducer operating at l MHz for use in cleaning semiconductor wafers or other industsrial materials is driven from the MOS-FET DC-to RF inverter, the output power severely depends on the frequency of operation since the quality factor of the transducer is high. In order to tune to the eresonating frequency of the ultrasonic transducer, the drive signal frequency of the MOS-FET power inverter is automatically scananed until the frequency is set at the resonating frequency of the ultrasonic transducer is maximized. The control circuit consists of an output power sensing circuit, a PLL controller, a frequency standard, and other peripheral circuits. The operation was satisfactory when the transducer having an output of 600 W at 1 MHz was used.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 1999.11a
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• pp.184-188
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• 1999

The power semiconductor switching devices(PSSD) continuously developed, Power Electronic Technology using PSSD is gradually extended. The high frequency inverter to generate the large power high frequency subject to power electronic technology pursuit various applications. Also, in emboss with environmental destruction problem cause the atmosphere and the water pollution to growth of the commercial society, the research in favor of cleaning environmental a pollutant actively proceed. Therefore, This paper describe study on the high frequency pulse power supply. The theoretical results are in good agreement with the experimental ones. The proposed pulse power supply is considerated to be useful for discharge lamp.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.611-615
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• 2003

In this paper, a operation characteristics and analysis of the HB(half bridge) inverter for remote plasma system are studied. the remote plasma system is cleaning system for the chemical vapor deposition (CVD) chamber in semiconductor processing. The remote plasma system is powered by the RF generator The main power stage of the RF generator is used for the HB PWM inverter with an low pass filter in the secondary circuit of the transformer. The detailed mode analysis of HB invertor was described. The operation characteristics of Remote Plasma Source are verified by simulation and experimental results.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.189-192
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• 2001

Recently, STI process is getting attention as a necessary technology for making high density of semiconductor by devices isolation method. However, it does have various problems caused by CMP nprocess, such as torn oxide defects, nitride residues on oxide, damages of si active region, contaminations due to post-CMP cleaning, difficulty of accurate end point detection in CMP process, etc. In this work, the various defects induced by CMP process was introduced and the above mentioned problems of CMP process was examined in detail. Finally, the guideline of future CMP process was presented to reduce the effects of these defects.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.6
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• pp.465-470
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• 2003

The chemical mechanical polishing (CMP) process has been widely used for the global planarization of multi-layer structures in semiconductor manufacturing. The CMP process can be optimized by several parameters such as equipment, consumables (pad, backing film and slurry), process variables and post-CMP cleaning. However, the COO(cost of ownership) is very high, because of high consumable cost. Especially, among the consumables, the slurry dominates more than 40 %. In this paper, we have studied the CMP characteristics of diluted silica slurry by adding of raw alumina abrasives and annealed alumina abrasives. As an experimental result, we obtained the comparable slurry characteristics compared with original silica slurry in the view-point of high removal rate and low non-uniformity. Therefore, we can reduce the cost of consumables(COC) of CMP process for ULSI applications.

• Proceedings of the Optical Society of Korea Conference
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• 2003.02a
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• pp.54-55
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• 2003

지금까지 반도체 장비 부품 세정을 위한 기존의 세정 방법중 가장 널리 사용되는 화학적 세정 방법은 다량의 유해 화학물질의 발생 및 후처리 문제, 비용문제, 열악한 작업 환경등과 같은 많은 문제를 노출시키고 있다. 이에 최근의 기술은 습식 세정에서 건식세정 방식으로의 기술 전이가 빠르게 이루어지고 있으며, 특히 레이저 광에 의한 건식 세정 기술은 다양한 오염 물질을 하나의 레이저 광원으로 제거할수 있으며, 기존의 습식 방법과 비교해 환경 친화적 청정 기술이고, 다른 건식 세정 기술인 드라이 아이스 및 플라즈마 세정 방법과 비교해 이동용으로 제작이 가능해 반도체 및 평판 디스플레이 생산공정에서 부품을 분리하지 않고 쉽게 세정을 하기 때문에 반도체 생산 현장에서 in-situ 세정으로 시간적, 경제적 이점이 대단히 크다. (중략)

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.189-192
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• 2001

Recently, STI process is getting attention as a necessary technology for making high density of semiconductor by devices isolation method. However, it does have various problems caused by CMP process, such as torn oxide defects, nitride residues on oxide, damages of si active region, contaminations due to post-CMP cleaning, difficulty of accurate end point detection in CMP process, etc. In this work, the various defects induced by CMP process was introduced and the above mentioned Problems of CMP process was examined in detail. Finally, the guideline of future CMP process was presented to reduce the effects of these defects.

• Journal of information and communication convergence engineering
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• v.1 no.2
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• pp.67-69
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• 2003

The experimental studies for the etch properties of the oxide grown on silicon substrate, which is in diluted hydrogen fluoride (HF) solution, are presented. Using different ion implantation dosages, dopants and energies, silicon substrate was implanted. The wet etching in diluted HF solution is used as a mean of wafer cleaning at various steps of VLSI processing. It is shown that the wet etch rate of oxide grown on various implanted silicon substrates is a strong function of ion implantation dopants, dosages and energies. This phenomenon has never been reported before. This paper shows that the difference of wet etch rate of oxide by ion implantation conditions is attributed to the kinds and volumes of dopants which was diffused out into $SiO_2$ from implanted silicon during thermal oxidation.

• Particle and aerosol research
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• v.9 no.4
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• pp.261-269
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• 2013

The chemical mechanical polishing (CMP) process is widely used in semiconductor manufacturing process for planarization of various materials and structures. Point-of-use (POU) filters are used in most of the CMP processes in order to reduce the unwanted micro-scratches which may result in defects. The performance of the POU filter is depends on type and size of the abrasives used during cleaning process. For this reason, there is a need to evaluate POU filters for their filtration efficiency (FE) with different types of abrasives. In this study, we developed filter test system to evaluate the FE of POU using ceria and silica abrasives (slurry). The POU filter is roll type capsule filter with retention size of 0.2 ${\mu}m$. Two POU filters of different make are evaluated for FE. We observed that both POU filters show similar filtration efficiency for silica and ceria slurry. Results reveal that the ceria slurry and the colloidal silica particle are removed not only by mechanical way but also hydrodynamic and electrostatic interaction way.