• Journal of Sensor Science and Technology
• /
• v.11 no.2
• /
• pp.77-83
• /
• 2002

In order to get low cost and portability, semiconductor gas sensor need to have low operating temperature and high sensitivity. $Fe_2O_3$ based sensors which were doped with metal oxide catalysts($MoO_3$, $V_2O_5$, $TiO_2$, and CdO) were fabricated by screen printing method. To improve electrical stability of sensors, the $Fe_2O_3$ sensors were annealed in $N_2$ at $700^{\circ}C$ for 2 hours. The $V_2O_5$ doped $Fe_2O_3$ sensor showed about $80{\sim}90%$ sensitivity at alcohol 1,000 ppm and have good selectivity to hydrocarbon gas and tobacco odors. The fabricated sensor and PIC-chip were employed for portable alarm system.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.21 no.12
• /
• pp.261-267
• /
• 2020

The demand for faster, lighter, and thinner portable electronic devices has brought about a change in semiconductor packaging technology. In response, a stacked chip-scale package(SCSP) is used widely in the assembly industry. One of the key materials for SCSP is a die-attach film (DAF). Excellent flowability is needed for DAF for successful die attachment without voids. For DAF with high flowability, two-step curing is often required to reduce a cure crack, but one-step curing is needed to reduce the processing time. In this study, DAF composition was categorized into three groups: cure (epoxy resins), soft (rubbers), hard (phenoxy resin, silica) component. The effect of the composition on a cure crack was examined when one-step curing was applied. The die-attach void and flowability were also assessed. The cure crack decreased as the amount of hard components decreased. Die-attach voids also decreased as the amount of hard components decreased. Moreover, the decrease in cure component became important when the amount of hard component was small. The flowability was evaluated using high-temperature storage modulus and bleed-out. A decrease in the amount of hard components was critical for the low storage modulus at 100℃. An increase in cure component and a decrease in hard component were important for the high bleed-out at 120℃(BL-120).

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.8
• /
• pp.54-61
• /
• 2001

A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage ($V_OL$) to be equal to the reference voltage ($V_{OL.ref}$) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1Gb/s. The worst-case variations of $V_{OL.ref}$ and $V_OL$ of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of $20^{\circ}C$ to $90^{\circ}C$ and a supply voltage range of 2.25V to 2.75V, while the worst-case variation of $V_OL$ of the conventional output driver was measured to be 24% at the same temperature and supply voltage ranges.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.239-240
• /
• 2012

With advancements in semiconductor device technologies, manufacturing processes are getting more complex and it became more difficult to maintain tighter process control. As the number of processing step increased for fabricating complex chip structure, potential fault inducing factors are prevail and their allowable margins are continuously reduced. Therefore, one of the key to success in semiconductor manufacturing is highly accurate and fast fault detection and classification at each stage to reduce any undesired variation and identify the cause of the fault. Sensors in the equipment are used to monitor the state of the process. The idea is that whenever there is a fault in the process, it appears as some variation in the output from any of the sensors monitoring the process. These sensors may refer to information about pressure, RF power or gas flow and etc. in the equipment. By relating the data from these sensors to the process condition, any abnormality in the process can be identified, but it still holds some degree of certainty. Our hypothesis in this research is to capture the features of equipment condition data from healthy process library. We can use the health data as a reference for upcoming processes and this is made possible by mathematically modeling of the acquired data. In this work we demonstrate the use of recurrent neural network (RNN) has been used. RNN is a dynamic neural network that makes the output as a function of previous inputs. In our case we have etch equipment tool set data, consisting of 22 parameters and 9 runs. This data was first synchronized using the Dynamic Time Warping (DTW) algorithm. The synchronized data from the sensors in the form of time series is then provided to RNN which trains and restructures itself according to the input and then predicts a value, one step ahead in time, which depends on the past values of data. Eight runs of process data were used to train the network, while in order to check the performance of the network, one run was used as a test input. Next, a mean squared error based probability generating function was used to assign probability of fault in each parameter by comparing the predicted and actual values of the data. In the future we will make use of the Bayesian Networks to classify the detected faults. Bayesian Networks use directed acyclic graphs that relate different parameters through their conditional dependencies in order to find inference among them. The relationships between parameters from the data will be used to generate the structure of Bayesian Network and then posterior probability of different faults will be calculated using inference algorithms.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.13 no.1
• /
• pp.64-71
• /
• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

• Journal of the Microelectronics and Packaging Society
• /
• v.28 no.3
• /
• pp.9-15
• /
• 2021

Miniaturization of semiconductor devices has recently faced a physical limitation. To overcome this, 3D packaging in which semiconductor devices are vertically stacked has been actively developed. 3D packaging requires three unit processes of TSV, wafer grinding, and bonding, and among these, copper bonding is becoming very important for high performance and fine-pitch in 3D packaging. In this study, the effects of Ti nanolayer on the antioxidation of copper surface and low-temperature Cu bonding was investigated. The diffusion rate of Ti into Cu is faster than Cu into Ti in the temperature ranging from room temperature to 200℃, which shows that the titanium nanolayer can be effective for low-temperature copper bonding. The 12nm-thick titanium layer was uniformly deposited on the copper surface, and the surface roughness (R_q) was lowered from 4.1 nm to 3.2 nm. Cu bonding using Ti nanolayer was carried out at 200℃ for 1 hour, and then annealing at the same temperature and time. The average shear strength measured after bonding was 13.2 MPa.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.6
• /
• pp.55-66
• /
• 2016

Power gating is one of effective techniques for reducing leakage current in semiconductor chip. However, power gating cell (PGC) which is used to switch the power source causes performance degradation and the associated reliability problem by increasing IR drop. However, the newly raised problem caused by different scaling properties between gates and metal wires demands additional considerations in power gating design. In this paper, we propose a robust cell placement based power gating design method for reducing the area for power gating cell and metal routing thus to meet IR drop requirement. Experimental results by applying the proposed techniques on the application processor for smartphone fabricated in 28nm CMOS process show that power gating cell area is reduced by 16.16% and maximum IR drop value is also decreased by 8.49% compared to existing power gating cell placement techniques.

• ETRI Journal
• /
• v.38 no.4
• /
• pp.665-674
• /
• 2016

We designed and fabricated a semiconductor optical amplifier-integrated dual-mode laser (SOA-DML) as a compact and widely tunable continuous-wave terahertz (CW THz) beat source, and a pin-photodiode (pin-PD) integrated with a log-periodic planar antenna as a CW THz emitter. The SOA-DML chip consists of two distributed feedback lasers, a phase section for a tunable beat source, an amplifier, and a tapered spot-size converter for high output power and fiber-coupling efficiency. The SOA-DML module exhibits an output power of more than 15 dBm and clear four-wave mixing throughout the entire tuning range. Using integrated micro-heaters, we were able to tune the optical beat frequency from 380 GHz to 1,120 GHz. In addition, the effect of benzocyclobutene polymer in the antenna design of a pin-PD was considered. Furthermore, a dual active photodiode (PD) for high output power was designed, resulting in a 1.7-fold increase in efficiency compared with a single active PD at 220 GHz. Finally, herein we successfully show the feasibility of the CW THz system by demonstrating THz frequency-domain spectroscopy of an ${\alpha}$-lactose pellet using the modularized SOA-DML and a PD emitter.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.1 no.4
• /
• pp.239-247
• /
• 2001

The Fluorescence-Activated Cell Sorter (FACS) is a well-established instrument used for identifying, enumerating, classifying and sorting cells by their physical and optical characteristics. For a miniaturized FACS device, a disposable plastic microchip has been developed which has a hydrodynamic focusing chamber using soft lithography. As the characteristics of the spatially confined sample stream have an effect on sample throughput, detection efficiency, and the accuracy of cell sorting, systematic fluid dynamic studies are required. Flow visualization is conducted with a laser scanning confocal microscopy (LSCM), and three-dimensional flow structure of the focused sample stream is reconstructed from 2D slices acquired at $1\mutextrm{m}$ intervals in depth. It was observed that the flow structure in the focusing chamber is skewed by unsymmetrical velocity profile arising from trapezoidal cross section of the microchannel. For a quantitative analysis of a microscopic flow structure, Confocal Micro-PIV system has been developed to evaluate the accelerated flow field in the focusing chamber. This study proposes a method which defines the depth of the measurement volume using a detection pinhole. The trajectories of red blood cells (RBCs) and their interactions with surrounding flow field in the squeezed sample stream are evaluated to find optimal shape of the focusing chamber and fluid manipulation scheme for stable cell transporting, efficient detection, and sorting

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.3
• /
• pp.189-195
• /
• 2004

A 10 Gb/s limiting amplifier IC with the emitter area of $1.5{\times}10{\mu}m^2$ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the $40{\mu}m$ diameter and $100{\mu}m$ pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to $600mV_{p-p}$ with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.