• 센서학회지
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• 제20권6호
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• pp.428-433
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• 2011

We report on the building of a micro sensor array based on typical semiconductor fabrication processes aimed at monitoring selectively a specific gas in ambient of other gases. Chemical sensors can be applied for an electronic nose and/or robots using this technique. Microsensor array was fabricated on the same chip using 0.6${\mu}m$ CMOS technology, and unique gas sensing patterns were obtained by principal component analysis from the array. $SnO_2$/Pt sensor for CO gas showed a high selectivity to buthane gas and humidity. $SnO_2$ sensor for hydrogen gas, however, showed a low selectivity to CO and buthane gas. We can obtain more distinguishable patterns that provide the small sensing deviation(the high seletivity) toward a given analyte in the response space than in the chemical space through the specific parameterization of raw data for chemical image formation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권4호
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• pp.275-280
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• 2006

We propose Doherty power amplifier structure which can be integrated in Silicon RF ICs. Doherty power amplifiers are widely used in RF transmitters, because of their high Power Added Efficiency (PAE) and good linearity. In this paper, it is proposed that a method to replace the quarter wavelength coupler with IQ up-conversion mixers to achieve 90 degree phase shift, which allows on-chip Doherty amplifier. This idea is implemented and manufactured in CMOS 5 GHz band direct-conversion RF transmitter. We measured a 3dB improvement output RF power and linearity.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권4호
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• pp.252-256
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• 2006

A low-power ECC check bit generator is presented with competent DRAM implementation with minimal speed loss, area overhead and power consumption. The ECC used in the proposed scheme is a variant form of the minimum weight column code. The spatial and temporal correlations of input data are analyzed and the input paths of the check bit generator are ordered for the on-line adaptable power savings up to 24.4% in the benchmarked cases. The chip size overhead is estimated to be under 0.3% for a 80nm 1Gb DRAM implementation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권2호
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• pp.114-118
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• 2006

In this paper, the effect of base and collector structures on DC, small signal characteristics of SiGe HBTs fabricated by RPCVD was investigated. The structure of SiGe HBTs was designed into four types as follows: SiGe HBT structures which are standard, apply extrinsic-base SEG selective epitaxial growth (SEG), apply selective collector implantation (SCI), and apply both extrinsic-base SEG and SCI. We verified the devices could be applied to the fabrication of RFIC chip through a fully integrated 2.4 GHz down-conversion mixer.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권2호
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• pp.75-79
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• 2009

A system-on-a-chip communication architecture has a significant impact on the performance and power consumption of modern multi-processors system-on-chips (MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus, system designers need tools to rapidly explore and evaluate communication architectures. In this paper we present the method for application-specific low-power bus architecture synthesis at system-level. Our paper has two contributions. First, we build a bus power model of AMBA AXI bus communication architecture. Second, we incorporate this power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the target bus architecture. The proposed exploration algorithm reduces power consumption by 20.1% compared to a maximally connected reduced matrix, and the area is also reduced by 20.2% compared to the maximally connected reduced matrix.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.241-246
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 $M{\sim}725$ MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권4호
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• pp.277-282
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• 2008

A fully integrated inductorless CMOS impulse radio ultra-wideband (IR-UWB) receiver is implemented using $0.18\;{\mu}m$ CMOS technology for 3-5 GHz application. The UWB receiver adopts the non-coherent architecture, which removes the complexity of RF architecture and reduces power consumption. The receiver consists of inductorless differential three stage LNA, envelope detector, variable gain amplifier (VGA), and comparator. The measured sensitivity is -70 dBm in the condition of 5 Mbps and BER of $10^{-3}$. The receiver chip size is only $1.8\;mm\;{\times}\;0.9\;mm$. The consumed current is 15 mA with 1.8 V supply.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.1957-1958
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• 2008

The Logic Built In Self Test (LBIST) technique is substantially applied in chip design in most many semiconductor company in despite of unavoidable overhead like an increase in dimension and time delay occurred as it used. Currently common LBIST software uses the MISR (Multiple Input Shift Register) However, it has many considerations like defining the X-value (Unknown Value), length and number of Scan Chain, Scan Chain and so on for analysis of result occurred in the process. So, to solve these problems, common LBIST software provides the solution method automated. Nevertheless, these problems haven't been solved automatically by Tri-state Bus in logic circuit yet. This paper studies the simulator and algorithm that judges whether Tri-state Bus lines is the circuit which have X-value or One-hot Value after presuming the control signal of the lines which output X-value in the logic circuit to solve the most serious problems.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2000년도 춘계학술대회논문집A
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• pp.873-878
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• 2000

Semiconductor packaging technology is changed rapidly according to the trends of the micro miniaturization of multimedia and information equipment. For I/O limitation and fine pitch limitation, DIP and SOP/QFP are replaced by BGA/CSP. This is one of the surface mount technology(SMT). Solder ball is bumped n the die pad and connected onto mounting board. In ball bump formation, vacuum suction type ball alignment process is widely used, However this type has some problems such as ionization, static electricity and difficulty of fifo(first-input first-out) of solder balls. Seesaw type is reducing these problems and has a structural simplicity and economic efficiency. Ball cartridge velocity and ball aligned plate angle are Important variables to improve the ball alignment Process. In this paper, seesaw-type CSP solder ball loader is developed and the optimal velocity and plate angle are proposed.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 1999년도 추계학술대회 논문집 - 한국공작기계학회
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• pp.502-506
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• 1999

Recently, the miniature of electric products such as notebook, cellular-phone etc. is apparently appeared, due to the smaller size of the semiconductor chips. As the size of chip gets smaller, the circuit could be easily damaged by the slightest influence, so it is important to control the chipping generation in the process of dicing. This paper deals with chipping of the silicon wafer dicing. The relationships between the dicing force and the wafer chipping are investigated. It is confirmed that the wafer chipping increases as the dicing force increases.