• Journal of Power Electronics
• /
• 제16권2호
• /
• pp.786-797
• /
• 2016

This paper describes the design and development of a novel semiconductor-based solid-state switch for damped oscillating voltage test system. The proposed switch is configured as two identical series-connected switch stacks, each of which comprising 10 series-connected IGBT function units. Each unit consists of one IGBT, a gate driver, and an auxiliary voltage sharing circuit. A single switch stack can block 20 kV-rated high voltage, and two stacks in series are proven applicable to 30 kV-rated high voltage. The turn-on speed of the switch is approximately 250 ns. A flyback topology-based power supply system with a front-end power factor correction is built for the drive circuit by loosely inductively coupling each unit with a ferrite core to the primary side of a power generator to obtain the advantages of galvanic isolation and compact size. After the simulation, measurement, and estimation of the parasitic effect on the gate driver, a prototype is assembled and tested under different operating regimes. Experimental results are presented to demonstrate the performance of the developed prototype.

• 대한전자공학회논문지SD
• /
• 제45권1호
• /
• pp.14-19
• /
• 2008

현대 반도체의 소형화 및 고성능화로 인해 반도체 테스팅 분야는 다양한 문제점에 봉착하고 있다. 이중 연결선에 대한 signal integrity 문제는 SoC와 같은 고집적 회로에서 반드시 해결해야할 문제이다. 본 논문에서는 연결선의 signal integrity 테스트를 위한 효과적인 테스트 패턴 적용 방안을 제안한다. 제안하는 테스트 패턴은 경계 주사 구조를 통해 적용 가능하며, 상당히 짧은 테스트 시간으로 매우 효과적인 테스트를 수행할 수 있다.

• 한국안전학회지
• /
• 제29권1호
• /
• pp.7-14
• /
• 2014

Inverter module, which feeds the converted power to the traction motor for EMU. Consists of the power semiconductors with their gate drive unit(GDU)s and the control computer for driving, voltage, current and speed controls. Electrolytic condenser, connected to the gate drive unit and a core component to drive the power semiconductor, has problems such as reduction in lifetime and malfunction caused by electrical and mechanical characteristic changes from heat generation during high speed switching for generation of stable power. In this study, To check the service life of electrolytic condenser, the test was carried out in two ways. First, In the case of accelerated life testing of condenser, the Arrhenius model is a way of life testing. Another way is to analyze the reliability of the failure data by the method of parametric data analysis. Eventually, life time by accelerated life test than a method of failure data analysis(Weibull distribution) was found to be slightly larger output.

• Genomics & Informatics
• /
• 제19권3호
• /
• pp.34.1-34.6
• /
• 2021

Digital PCR (dPCR) is the third-generation PCR that enables real-time absolute quantification without reference materials. Recently, global diagnosis companies have developed new dPCR equipment. In line with the development, the Lab On An Array (LOAA) dPCR analyzer (Optolane) was launched last year. The LOAA dPCR is a semiconductor chip-based separation PCR type equipment. The LOAA dPCR includes Micro Electro Mechanical System that can be injected by partitioning the target gene into 56 to 20,000 wells. The amount of target gene per wells is digitized to 0 or 1 as the number of well gradually increases to 20,000 wells because its principle follows Poisson distribution, which allows the LOAA dPCR to perform precise absolute quantification. LOAA determined region of interest first prior to dPCR operation. To exclude invalid wells for the quantification, the LOAA dPCR has applied various filtering methods using brightness, slope, baseline, and noise filters. As the coronavirus disease 2019 has now spread around the world, needs for diagnostic equipment of point of care testing (POCT) are increasing. The LOAA dPCR is expected to be suitable for POCT diagnosis due to its compact size and high accuracy. Here, we describe the quantitative principle of the LOAA dPCR and suggest that it can be applied to various fields.

• Journal of Magnetics
• /
• 제7권3호
• /
• pp.101-105
• /
• 2002

MRAM (Magnetoresistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-volatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnel Junction) as a data storage part and MOS transistor as a data selection part. This paper is for testing the actual electrical parameters to adopt MRAM technology in the semiconductor based memory device. The discussed topics are an actual integration of MRAM core cell and its properties such as electrical tuning of MOS/MTJ for data sensing and control of magnetic switching for data writing. It will be also tested that limits of the MRAM technology for a high density memory.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2004년도 전력전자학술대회 논문집(1)
• /
• pp.249-253
• /
• 2004

This paper presents an implementation of position control system of Switched Reluctance Motor (SRM) using digital hysteresis controller. Although SRM possess several advantages including simple structure and high efficiency, the control drive system using power semiconductor device is required to drive this motor. The control drive system increases overall system cost. To overcome this problem and increase the application of SRM, it is needed to develope the servo drive system of SRM. So, the position control system of 1 Hp SRM is developed and evaluated by adaptive switching angle control. The position/speed response characteristics and voltage/current waveforms are presented to prove the capability of SRM for a servo drive application. Moreover, digital hysteresis current controller is developed and evaluated by experimental testing for the purpose of system developmental cost reduction.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제16권5호
• /
• pp.582-594
• /
• 2016

Various test data compression techniques have been developed to reduce the test costs of system-on-a-chips. In this paper, a scan chain reordering algorithm for code-based test data compression techniques is proposed. Scan cells within an acceptable relocation distance are ranked to reduce the number of conflicts in all test patterns and rearranged by a positioning algorithm to minimize the routing overhead. The proposed method is demonstrated on ISCAS '89 benchmark circuits with their physical layout by using a 180 nm CMOS process library. Significant improvements are observed in compression ratio and test power consumption with minor routing overhead.

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 1997년도 추계학술대회 논문집
• /
• pp.865-869
• /
• 1997

In recent years, there has been increasing demand of ultra-fine grain graded cemented tungsten carbide material with high hardness and toughness which is used as high speed cutting tool for development in semiconductor, electronics and die/mold industry, which bring into limelight high-precision, high-efficient machining of sculptured surfaces. This paper deals with the performance of variation in the ultra-fine grain graded cemented tungsten carbide material such as grain size, hardness and density varied according to the volume of added elements, Co or TaC, and he changing of mixing, sintering process. Also, the performance of developing material with uniformed grain size of 0.5${\mu}{\textrm}{m}$ is compared with other domestics' & foreign companies' with analyzing and cutting performance testing.

• International Journal of Fluid Machinery and Systems
• /
• 제1권1호
• /
• pp.92-100
• /
• 2008

The main objective of this study was to clarify the origin of the unsteady flows arising in a mixed-flow vaneless diffuser system and also the effects of physical components of the system. The testing equipment consists of a straight tube, a swirl generator, and a mixed-flow vaneless diffuser. Pressure fluctuations of the flow through the tube and diffuser were measured by using a semiconductor-type pressure transducer and analyzed by an FFT analyzer. In the experiment, the velocity ratio (axial velocity/peripheral velocity) of the internal flow, and the geometric parameters of the diffuser were varied. Two kinds of unsteady flows were measured according to the combination of the components, and the origin of each unsteady flow was clarified. The fundamental frequencies of unsteady flows arose were examined by two-dimensional small perturbation analysis.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제3권3호
• /
• pp.122-131
• /
• 2003

In this study, some characteristics of conductive and non-conductive adhesive inter-connections are derived, based on data from literature and own projects. Assembly of flip chip on flex is taken as a carrier. Potential failure mechanisms of adhesive interconnections reported in literature are reviewed. Some methods that can be used to evaluate the quality of adhesive interconnections and to evaluate their aging behavior are given. Possible finite element simulation approaches are introduced and the required critical materials properties are summarized. Response to temperature and moisture, resistance to reflow soldering and resistance to rapid change in temperature and humidity are elaborated. The effect of post cure during accelerated testing is discussed. This study shows that only a combined approach using finite element simulations, and use of appropriate experimental evaluation methods can result in revealing, understanding and quantifying the complex degradation mechanisms of adhesive interconnections during aging.