• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.2
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• pp.27-32
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• 2010

This paper suggests the new performance evaluation system which is suitable for high speed EFEM(Equipment Front End Module) device using a semiconductor process. An EFEM consisting of multi-joint robots is the mainstay of semiconductor automation, shuffling silicon wafers or quartz photo-masks between ultra-clean storage carriers and a variety of processing, measurement and testing systems. The theoretical and experimental studies for the development of performance evaluation system have been carried out. The presented results from the above investigation show considerably developed performance evaluation system for the high speed EFEM Especially, it is efficient for prepareing the WTO/TBT(Technical Barriers to Trade) Agreement and the PL(Product Liability) law.

• Journal of the Korean Society for Nondestructive Testing
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• v.36 no.1
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• pp.18-26
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• 2016

The semiconductor industry is one of the key industries of Korea, which has continued growing at a steady annual growth rate. Important technology for the semiconductor industry is high integration of devices. This is to increase the memory capacity for unit area, of which key is photolithography. The photolithography refers to a technique for printing the shadow of light lit on the mask surface on to wafer, which is the most important process in a semiconductor manufacturing process. In this study, the width and step-height of wafers patterned through this process were measured to ensure uniformity. The widths and inter-plate heights of the specimens patterned using photolithography were measured using transmissive digital holography. A transmissive digital holographic interferometer was configured, and nine arbitrary points were set on the specimens as measured points. The measurement of each point was compared with the measurements performed using a commercial device called scanning electron microscope (SEM) and Alpha Step. Transmission digital holography requires a short measurement time, which is an advantage compared to other techniques. Furthermore, it uses magnification lenses, allowing the flexibility of changing between high and low magnifications. The test results confirmed that transmissive digital holography is a useful technique for measuring patterns printed using photolithography.

• ETRI Journal
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• v.39 no.6
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• pp.866-873
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• 2017

We propose a multilayered-substrate-based power semiconductor discrete device package for a low switching loss and high heat dissipation. To verify the proposed package, cost-effective, low-temperature co-fired ceramic, multilayered substrates are used. A bare die is attached to an embedded cavity of the multilayered substrate. Because the height of the pad on the top plane of the die and the signal line on the substrate are the same, the length of the bond wires can be shortened. A large number of thermal vias with a high thermal conductivity are embedded in the multilayered substrate to increase the heat dissipation rate of the package. The packaged silicon carbide Schottky barrier diode satisfies the reliability testing of a high-temperature storage life and temperature humidity bias. At $175^{\circ}C$, the forward current is 7 A at a forward voltage of 1.13 V, and the reverse leakage current is below 100 lA up to a reverse voltage of 980 V. The measured maximum reverse current ($I_{RM}$), reverse recovery time ($T_{rr}$), and reverse recovery charge ($Q_{rr}$) are 2.4 A, 16.6 ns, and 19.92 nC, respectively, at a reverse voltage of 300 V and di/dt equal to $300A/{\mu}s$.

• KIISE Transactions on Computing Practices
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• v.21 no.10
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• pp.645-650
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• 2015

Tester Interface Software (TIS) provides all software functions that are necessary for a testing device to perform the test process on a memory semiconductor package from the time the device is put into the test equipment until the device is discharged from the equipment. TIS should perform the same work over all types of equipment regardless of their tester models. However, TIS has been developed and managed independently of the tester models because there are various equipment and computer models that are used in the test process. Therefore, more maintenance, time and cost are required for development, which adversely affects the quality of the software, and the problem becomes more serious when the new tester model is introduced. In this paper, we propose the Cross-platform Tester Interface Software (CTIS) framework, which can be integrated and operated on heterogeneous equipment and OSs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.640-648
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• 2014

Excessive power dissipation is one of the major issues in the testing of VLSI systems. Many techniques are proposed for scan test, but there are not so many for logic BIST because of its unmanageable randomness. This paper presents a novel low switching activity BIST scheme that reduces toggle frequency in the majority of scan chain inputs while allowing a small portion of scan chains to receive pseudorandom test data. Reducing toggle frequency in the scan chain inputs can reduce test power but may result in fault coverage loss. Allowing a small portion of scan chains to receive pseudorandom test data can make better uniform distribution of 0 and 1 and improve test effectiveness significantly. When compared with existing methods, experimental results on larger benchmark circuits of ISCAS'89 show that the proposed strategy can not only reduce significantly switching activity in circuits under test but also achieve high fault coverage.

• Journal of the Korean Society for Nondestructive Testing
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• v.29 no.6
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• pp.550-556
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• 2009

In an application of a time reversal(TR) focusing of array transducer on a defect inside the test material, we employ a new time delay focusing technique based the TR process. In order to realize this idea, a multi-channel ultrasonic system is constructed capable of applying necessary time delays to each channel. The TR-based focusing procedure first measures the backscattered signals after firing one of the array elements. A phase slope method is then used to determine the time-of-flights of the backscattered signals received by all elements of the array. These time delays are used to adjust the time of excitation of the elements for transmission focusing on the defect. In addition to the TR focusing, the classical phased array focusing is also considered for comparison. Experimental results show that the TR-based time delay focusing produces much stronger backscattered signals than the phased array focusing, demonstrating the enhanced capability of the TR focusing.

• Journal of the Korean Society for Nondestructive Testing
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• v.27 no.3
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• pp.246-254
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• 2007

The scanning laser source (SLS) technique is a promising new laser ultrasonic tool for the detection of small surface-breaking defects. The SLS approach is based on monitoring the changes in laser-generated ultrasound as a laser source is scanned over a defect. Changes in amplitude and frequency content are observed for ultrasound generated by the laser over uniform and defective areas. The SLS technique uses a point or a short line-focused high-power laser beam which is swept across the test specimen surface and passes over surface-breaking or subsurface flaws. The ultrasonic signal that arrives at the Rayleigh wave speed is monitored as the SLS is scanned. It is found that the amplitude and frequency of the measured ultrasonic signal have specific variations when the laser source approaches, passes over and moves behind the defect. In this paper, the setup for SLS experiments with full B-scan capability is described and SLS signatures from small surface-breaking and subsurface flaws are discussed using a point or short line focused laser source.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.186-193
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• 2003

In recent years the complexity of digital systems has increased dramatically. Although semiconductor manufacturers try to ensure that their products are reliable, it is almost impossible not to have faults somewhere in a system at any given time. As complexity of circuits increases, the necessity of more efficient organized and automated methods for test generation is growing. But, up to now, most of popular and extensive methods for test generation nay be those which sequentially produce an output for an input pattern. They inevitably require a lot of time to search each fault in a system. In this paper, corresponding test patterns are generated through the partitioning method among those based on the exhaustive method. In addition, the method, which can discovers faults faster than other ones that have been proposed ever by inserting a pattern in parallel, is designed and implemented.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.713-718
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• 2016

Predicting precise specifications of differential mixed-signal circuits is a difficult problem, because analytically derived correlation between process variations and conventional specifications exhibits the limited prediction accuracy due to the phase unbalance, for most self-tests. This paper proposes an efficient prediction technique to provide accurate specifications of differential mixed-signal circuits in a system-on-chip (SoC) based on a nonlinear statistical nonlinear regression technique. A spectrally pure sinusoidal signal is applied to a differential DUT, and its output is fed into another differential DUT through a weighting circuitry in the loopback configuration. The weighting circuitry, which is employed from the previous work [3], efficiently produces different weights on the harmonics of the loopback responses, i.e., the signatures. The correlation models, which map the signatures to the conventional specifications, are built based on the statistical nonlinear regression technique, in order to predict accurate nonlinearities of individual DUTs. In production testing, once the efficient signatures are measured, and plugged into the obtained correlation models, the harmonic coefficients of DUTs are readily identified. This work provides a practical test solution to overcome the serious test issue of differential mixed-signal circuits; the low accuracy of analytically derived model is much lower by the errors from the unbalance. Hardware measurement results showed less than 1.0 dB of the prediction error, validating that this approach can be used as production test.

• Journal of the Korean Society for Nondestructive Testing
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• v.28 no.2
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• pp.151-156
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• 2008

Many kinds of mass spectrometer type leak detectors have been widely used for detecting leak of vacuum processes in semiconductor and display industries etc. The leak detectors should be often calibrated by the permeation type standard leak in order to ensure accurate and reproducible leak measurement. We have developed a comparative calibration system for permeation type standard leak by using mass spectrometer type leak detector and specification of the calibration method. Following this technique the reliable calibration for leak standard ran be performed even in fields.