An Efficient Parallel Testing using The Exhaustive Test Method

Exhaustive 테스트 기법을 사용한 효율적 병렬테스팅

  • 김우완 (경상대학교 정보통신공학부)
  • Published : 2003.04.01

Abstract

In recent years the complexity of digital systems has increased dramatically. Although semiconductor manufacturers try to ensure that their products are reliable, it is almost impossible not to have faults somewhere in a system at any given time. As complexity of circuits increases, the necessity of more efficient organized and automated methods for test generation is growing. But, up to now, most of popular and extensive methods for test generation nay be those which sequentially produce an output for an input pattern. They inevitably require a lot of time to search each fault in a system. In this paper, corresponding test patterns are generated through the partitioning method among those based on the exhaustive method. In addition, the method, which can discovers faults faster than other ones that have been proposed ever by inserting a pattern in parallel, is designed and implemented.

최근 몇 년 동안 디지털 시스템이 복잡성은 아주 빠르게 증가하고 있다. 비록 반도체 제조업자들이 제품에 대한 신뢰성을 높이려고 노력하고 있지만 어느 때에 시스템이 어딘가에서 결함이 발생할 것이라는 것을 알기는 불가능하다. 이렇듯이 회로가 복잡화함에 따라 테스트 생성(test generation)에 대한 잘 정리되어 있고 자동화된 방법이 필요하게 되었다. 하지만 현재 광범위하게 사용하고 있는 방법중 대부분은 한번에 하나씩의 패턴만을 넣어서 처리하는 방식이다. 이는 각각의 결함에 대해서 탐색하는데 많은 시간을 낭비하게 된다. 본 논문에서는 Exhaustive 방법을 사용하는 테스트 패턴 생성 방법 중에서 분할 기법을 적용하여 테스트 패턴을 생성한다. 또한 이 패턴을 이용하여 병렬로 패턴을 삽입함으로써 더욱 빠르게 결함을 발견할 수 있는 방법을 설계 및 구현한다.

Keywords

References

  1. Parag K. Lala, Fault Tolerant and fault testable hardware design , Prentice Hall International, New York, New York, 1985
  2. Grabriel M. Seiberman, and Han Spillinger, 'Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation,' IEEE Transactions on Computer, VOL. 40, NO. 1 January 1991 https://doi.org/10.1109/12.67321
  3. S.P. Tomas, and J.P. Shen, 'A survey of: functional level testing and testability measures,' Res. Rep. CMUCAD-83-18, Carnegi-Mellon Univ., Pittsburgh, PA, 1983
  4. Janusz Rajski, and Jerzy Tyszer, 'Recursive Pseudoexhaustive Test Pattern Generation,' IEEE Transactions on Computer, VOL. 42, NO. 12, December 1993 https://doi.org/10.1109/12.260644
  5. A.K. Das, A. Sanyal, and P. Pal Chaudhuri, 'On characterization of cellular automata with matrix algebra,' Inform. Sci., vol. 65, pp 251-277, June 1992 https://doi.org/10.1016/0020-0255(92)90053-B
  6. M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design. Computer Science Press, New York, New York, 1990
  7. E,J. McCluskey, 'Verification testing A pseudoexhaustive test technique,' IEEE Trans. Comput. Vol. C-33, pp. 541-546, June 1984 https://doi.org/10.1109/TC.1984.1676477
  8. G.E. Sobelman, and C.H. Chen, 'An efficient approach to pseudoexhaustive test generation for BIST design,' in Proc. ICCD, 1989, pp. 576-579
  9. Anderson, Tand P. Lee, Fault-tolerance. principle and practice, Prentice-Hall International, New York, New York, 1981
  10. Dhiraj K. Pradahan, Fault-Tolerant Computing, Prentice-Hall, Englewood Cliffs, New Jersey, 1986
  11. Sellers, F.F, MoYo Hsiao and C.L. Beamson, 'Analyzing errors with the Boolean difference,' IEEE Trans. Comput., pp. 676-683 July 1968 https://doi.org/10.1109/TC.1968.227417
  12. K.P. Parker and E.J. McCluskey, 'Probablistic Treatment of General Combinational Networks,' IEEE Trans. Computers, Vol. 24, No.6, pp668-670, June 1975 https://doi.org/10.1109/T-C.1975.224279
  13. Dhiraj K. Pradahan, Fault-Tolerant Computer System Design, Prentice-Hall International, New York, New York, 1993
  14. M.H. Konijnenburg, A.J. Van De Goor, and J.Th. Van der Linden, 'Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Ristrictors,' 5th Asian Test Symposium(ATS '96), pp29-33, Nov. 1996
  15. Douglas Chang, and malgorzata Marek-Sadowska, 'Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs,' IEEE Transactions on Computers, pp565-578, June 1999 https://doi.org/10.1109/12.773794
  16. D.J.Huang, and A.B. Kahng, 'When Clusters Meet Partitions: New Density-Based Methods for Circuit Decomposition,' Proc. of EDTC, pp60-64, March 1995 https://doi.org/10.1109/EDTC.1995.470419
  17. Kristian Wiklund, 'A gate Level Fault Simulation Toolkit,' Charmers University of Technonology, Gothenburg, Sweden, Tech. Report 00-17, 2001