Browse > Article

An Efficient Parallel Testing using The Exhaustive Test Method  

김우완 (경상대학교 정보통신공학부)
Abstract
In recent years the complexity of digital systems has increased dramatically. Although semiconductor manufacturers try to ensure that their products are reliable, it is almost impossible not to have faults somewhere in a system at any given time. As complexity of circuits increases, the necessity of more efficient organized and automated methods for test generation is growing. But, up to now, most of popular and extensive methods for test generation nay be those which sequentially produce an output for an input pattern. They inevitably require a lot of time to search each fault in a system. In this paper, corresponding test patterns are generated through the partitioning method among those based on the exhaustive method. In addition, the method, which can discovers faults faster than other ones that have been proposed ever by inserting a pattern in parallel, is designed and implemented.
Keywords
Exhaustive Test; Parallel Testing; Circuit Partitioning;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Parag K. Lala, Fault Tolerant and fault testable hardware design , Prentice Hall International, New York, New York, 1985
2 Grabriel M. Seiberman, and Han Spillinger, 'Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation,' IEEE Transactions on Computer, VOL. 40, NO. 1 January 1991   DOI   ScienceOn
3 S.P. Tomas, and J.P. Shen, 'A survey of: functional level testing and testability measures,' Res. Rep. CMUCAD-83-18, Carnegi-Mellon Univ., Pittsburgh, PA, 1983
4 Janusz Rajski, and Jerzy Tyszer, 'Recursive Pseudoexhaustive Test Pattern Generation,' IEEE Transactions on Computer, VOL. 42, NO. 12, December 1993   DOI   ScienceOn
5 E,J. McCluskey, 'Verification testing A pseudoexhaustive test technique,' IEEE Trans. Comput. Vol. C-33, pp. 541-546, June 1984   DOI   ScienceOn
6 G.E. Sobelman, and C.H. Chen, 'An efficient approach to pseudoexhaustive test generation for BIST design,' in Proc. ICCD, 1989, pp. 576-579
7 Anderson, Tand P. Lee, Fault-tolerance. principle and practice, Prentice-Hall International, New York, New York, 1981
8 A.K. Das, A. Sanyal, and P. Pal Chaudhuri, 'On characterization of cellular automata with matrix algebra,' Inform. Sci., vol. 65, pp 251-277, June 1992   DOI   ScienceOn
9 Sellers, F.F, MoYo Hsiao and C.L. Beamson, 'Analyzing errors with the Boolean difference,' IEEE Trans. Comput., pp. 676-683 July 1968   DOI
10 K.P. Parker and E.J. McCluskey, 'Probablistic Treatment of General Combinational Networks,' IEEE Trans. Computers, Vol. 24, No.6, pp668-670, June 1975   DOI   ScienceOn
11 Dhiraj K. Pradahan, Fault-Tolerant Computer System Design, Prentice-Hall International, New York, New York, 1993
12 M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design. Computer Science Press, New York, New York, 1990
13 M.H. Konijnenburg, A.J. Van De Goor, and J.Th. Van der Linden, 'Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Ristrictors,' 5th Asian Test Symposium(ATS '96), pp29-33, Nov. 1996
14 Douglas Chang, and malgorzata Marek-Sadowska, 'Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs,' IEEE Transactions on Computers, pp565-578, June 1999   DOI   ScienceOn
15 Dhiraj K. Pradahan, Fault-Tolerant Computing, Prentice-Hall, Englewood Cliffs, New Jersey, 1986
16 D.J.Huang, and A.B. Kahng, 'When Clusters Meet Partitions: New Density-Based Methods for Circuit Decomposition,' Proc. of EDTC, pp60-64, March 1995   DOI
17 Kristian Wiklund, 'A gate Level Fault Simulation Toolkit,' Charmers University of Technonology, Gothenburg, Sweden, Tech. Report 00-17, 2001