• Proceedings of the Korea Society for Simulation Conference
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• 2002.05a
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• pp.145-149
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• 2002

92∼3년 A 라인에서 처음으로 Bay 내에 Conveyor (Intra) 사용한 Stocker to Equipment에서 Material(Lot) Moving을 위한 Project를 실시하였으나 예상과는 달리 Conveyor Capability가 부족하여 장비에서 Rundown 현상이 발생하였다. 정상적인 Simulation없이 Design한 Conveyor System은 막대한 금전투자, 인력투자, 설치Testing 철거 등으로 인한 라인 작업방해 등 막대한 손실을 남기는 실패를 가져왔다. 본 연구에서는 이미 장비가 Setup되어 Running중에 있는 반도체 라인 환경 또는 신규로 새로운 라인을 Design할 때 사람을 대신하여 Bay내에서 Lot을 Stocker에서 장비 또는 장비에서 장비로 이동을 Conveyer를 사용할 경우 적정 Conveyor Capability를 산정 하는데 그 목적이 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.213-223
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• 2013

A unified channel thermal noise model valid in all operation regions is presented for short channel MOS transistors. It is based on smooth interpolation between weak and strong inversion models and consistent physical model including velocity saturation, channel length modulation, and carrier heating. From testing for noise benchmark and comparing with published noise data, it is shown that the proposed noise model could be useful in simulating the MOSFET channel thermal noise in all operation regions.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.55.4-55
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• 2002

In the semiconductor fabrication, particle contamination is wide-spread and one of major causes to yield loss. Extensive testing has revealed that even careful handling of wafers during processing may cause photo-resist materials to flake off wafer edges. So, to remove the photo-resist at the outer 5mm of wafers, UV(Ultraviolet) rays are exposed. WEE (Wafer Edge Exposure) process station is the system that exposes the wafer edge as prespecified by controlling the positioning mechanism and maintaining the light intensity level In this work, WEE process station has been designed so as to significantly lower the amount of particle contamination which occurs even during the most r...

• 제어로봇시스템학회:학술대회논문집
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• 1998.10a
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• pp.480-483
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• 1998

For memory products, it is very important to develop a new production line as soon as possible. All products are inspected to get rid of defected products at the last testing stage. Those inspection data are called FCM. In this paper, based on the FCM data, Area Usage Factor (AUF) analyzing method will be proposed. Process engineers can make up their mind to which direction they should concentrate their analyzing power.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.1
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• pp.327-332
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• 2021

At the package level, semiconductor reliability inspections involves mounting a semiconductor chip package on a test socket. The form of the test socket is basically determined by the form of the chip package. It also acts as a medium to connect with test equipment through mechanical contact of the leads and socket leads in the chip package, and it minimizes signal loss in a signal transmission process so that an inspection signal can be delivered well to the semiconductor. In this study, a technique was applied to examine the interdependence of adjacent electrical transfer routes and the structure of adjacent electrical transfer paths. The goal was to enable short-circuit testing of fewer than 100 silicon test sockets through a single interface for life tests and precision measurements. The test results of the developed device show a test precision of 99% or more and a simultaneous test speed characteristic of 0.66 sec or less.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.11
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• pp.981-987
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• 2014

DC/DC switching power converters are commonly used to generate a regulated DC output voltage with high efficiency. The DC/DC converter is composed of a MOSFET (metal-oxide semiconductor field effect transistor), a PWM-IC (pulse width modulation-integrated circuit) controller, inductor, capacitor, etc. It is shown that the variation of threshold voltage and the breakdown voltage in the electrical characteristics of MOSFET occurs by radiation effects in TID (Total Ionizing Dose) testing at the low energy ${\gamma}$ rays using $^{60}Co$, and 5 heavy ions make the gate of MOSFET broken in SEGR (Single Event Gate Rupture) testing. TID testing on MOSFET is accomplished up to the total dose of 40 krad, and the cross section($cm^2$) versus LET(MeV/mg/$cm^2$) in the MOSFET operation is studied at SEGR testing after implementation of the controller board.

• Journal of the Korean Society of Radiology
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• v.11 no.3
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• pp.101-108
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• 2017

DC/DC switching power converters are commonly used to generate a regulated DC output voltage with high efficiency. The advanced DC/DC converter uses a PWM-IC with OP-Amp. (Operational Amplifier) to control a MOSFET (metal-oxide semiconductor field effect transistor), which is a switching component, efficiently. In this paper, it is shown that the electrical characteristics of OP-Amp. are affected by radiations of ${\gamma}$ rays using $^{60}Co$ for TID (Total Ionizing Dose) testing and 5 heavy ions for SEL (Single Event Latch-up) testing. TID testing on OP-Amp. is accomplished up to the total dose of 30 krad, and the cross section($cm^2$) versus LET($MeV/mg/cm^2$) in the OP-Amp. operation is evaluated SEL testing after implementation of the controller board.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.266-276
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• 2001

Due to the rapid development of semiconductor technology, the complexity of VLSI circuits has heavily increased. With the increased densities of integrated circuits, several different types of faults can occur Thus, testing such circuits is becoming a sever problem. Delay testing can detect system timing failures caused by delay faults. However, the conventional delay fault coverage in terms of the number of detected faults may not be an effective measure of delay testing because, unlike a stuck-at-faults, the impact of a delay fault is dependent on its delay defect size rather than on its existence. Thus, the effectiveness of delay testing is dependent on the propagation delay of the path to be tested, the delay defect size, and the system clock interval. This paper proposes a new delay defect fault coverage that considers both propagation delay of the path to be tested and additional delay defect size. And the relationship between delay defect fault coverage and defect level is analyzed.

• Journal of the Korean Society for Nondestructive Testing
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• v.20 no.6
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• pp.511-520
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• 2000

Ultrasonic pulse echo method comes to be difficult to apply to the multi-layered structure with very thin layer, because the echoes from the top and the bottom of the layer are superimposed. We can easily meet this problem when the silicon chip layer in the semiconductor is inspected by a SAM equipment using fairly low frequency lower than 20MHz by which severe attenuation in the epoxy mold compound of packaging material can be overcome. Conventionally, deconvolution technique has been used for the decomposition of superimposed UT signals, however it has disabilities when the waveform of the transmitted signal is distorted according to the propagation. In this paper, the wavelet transform based deconvolution(WTBD) technique is proposed as a new signal processing method that can decompose the superimposed echo signals with superior performances compared to the conventional deconvolution technique. WTBD method uses the wavelet transform in the pre-stage of deconvolution to extract out the common waveform from the transmitted and received signal with distortion. Performances of the proposed method we shown by through computer simulations using model signal with noise and we demonstrated by through experiments for the fabricated semiconductor sample with partial delamination at the top of silicon chip layer.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.41 no.1
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• pp.79-84
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• 2013

DC/DC switching power converters are commonly used to generate a regulated DC output voltage with high efficiency. The DC/DC converter is composed of a PWM-IC (pulse width modulation-integrated circuit) controller, a MOSFET (metal-oxide semiconductor field effect transistor), inductor, capacitor, etc. It is shown that the variation of threshold voltage and the offset voltage in the electrical characteristics of PWM-IC increase by radiation effects in TID (Total Ionizing Dose) testing at the low energy ${\gamma}$ rays using $^{60}Co$, and 4 heavy ions applied for SEL (Single Event Latch-up) make the PWM pulse unstable. Also, the output waveform for the given input in the DC/DC converter is observed by the simulation program with integrated circuit emphasis (SPICE). TID testing on PWM-IC is accomplished up to the total dose of 30 krad, and the cross section($cm^2$) versus LET($MeV/mg/cm^2$) in the PWM operation is studied at SEL testing after implementation of the controller board.