• 반도체디스플레이기술학회지
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• 제14권2호
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• pp.67-72
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• 2015

For the development of UFS device test system, M-PHY specifications should be matched with MIPI-standard which is analog signal protocol. In this paper, the implementation methodology and hardware structure for the M-PHY AFE (Analog Front End) Block was suggested that it can be implemented using universal components without ASIC process. The testing procedure has a jitter problem so to solve the problems we using ASIC process, normally but the ASIC process needs a lot of developing cost making the UFS device test system. In is paper, the suggestion was verified by the output signal which was compared to the MIPI-standard on the Prototype-board using universal components. The board was reduced the jitter on the condition of HS-TX and 5.824 Gbps Mode in SerDes (Serialize-deserializer). Finally, the suggestion and developed AFE block have a useful better than ASIC process on developing costs of the industrial UFS device test system.

• 반도체디스플레이기술학회지
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• 제19권2호
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• pp.82-87
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• 2020

In this paper, we introduce the novel idea to improve the B/W usage efficiency of on-chip networks used for TAM to test multiple DRAMs. In order to avoid the local bottleneck of test packets caused by an ATE, we make test patterns using microcode-based instructions within ATE and adopt a test bus to transmit test responses from DRAM DFT (Design for Testability) called Test Generator (TG) to ATE. The proposed test platform will contribute to increasing the test economics of memory IC industry.

• 반도체디스플레이기술학회지
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• 제18권4호
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• pp.143-148
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• 2019

Numerous pipe lines can be found on various plant-based industrial sites. These pipelines should be periodically checked for defects. Most of these pipelines are internally inaccessible and difficult to visually inspect. Therefore, the inspection is being carried out with the help of non-contact inspection equipment such as ultrasonic flaw detection equipment. The use of ultrasonic flaw detection equipment can raise time and efficiency issues. In order to solve this problem, we will study the basic technology necessary for the development of automated inspection system equipped with ultrasonic measuring equipment and verify the validity through the fabrication of the demonstration device.

• 반도체디스플레이기술학회지
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• 제19권4호
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• pp.126-129
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• 2020

We introduce a lifetime assessment technique using deep learning algorithm with complex electrical parameters such as resistivity, permittivity, impedance parameters as integrated indicators for predicting the degradation of the organic molecules. The evaluation system consists of fully automated in-situ measurement system and multiple layer perceptron learning system with five hidden layers and 1011 perceptra in each layer. Prediction accuracies are calculated and compared depending on the physical feature, learning hyperparameters. 62.5% of full time-series data are used for training and its prediction accuracy is estimated as r-square value of 0.99. Remaining 37.5% of the data are used for testing with prediction accuracy of 0.95. With k-fold cross-validation, the stability to the instantaneous changes in the measured data is also improved.

• 반도체디스플레이기술학회지
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• 제22권1호
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• pp.49-53
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• 2023

In this paper, we propose an antirandom pattern-based test method considering power consumption to compensate for the problem that the fault coverage through random test decreases or the test time increases significantly when the DUT circuit structure is complex or large. In the proposed method, a group unit test pattern generation process and rearrangement process are added to improve the problems of long calculation time and high-power consumption, which are disadvantages of the previous antirandom test.

• 반도체디스플레이기술학회지
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• 제21권4호
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• pp.23-26
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• 2022

In this paper, our ray tracing hardware is implemented on the latest high-capacity FPGA board. The system included ray tracing hardware for rendering and tree building hardware for handling dynamic scenes. The FPGA board used in the implementation is a Xilinx Alveo U250 accelerator card for data centers. This included 12 ray tracing hardware cores and 1 tree-building hardware core. As a result of testing in various scenes in Full HD resolution, the FPS performance of the proposed ray tracing system was measured from 8 to 28. The overall average is about 17.7 FPS.

• 반도체디스플레이기술학회지
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• 제22권3호
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• pp.136-141
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• 2023

Artificial intelligence is becoming a global hot topic and is being actively applied in various industrial fields. Not only is artificial intelligence being applied to industrial sites in an on-premises method, but cloud-based artificial intelligence platforms are expanding into "as a service" type. The purpose of this study is to develop and verify a measurement tool for an evaluation framework for the adoption of a cloud-based artificial intelligence platform and test the interrelationships of evaluation variables. To achieve this purpose, empirical testing was conducted to verify the hypothesis using an expanded technology acceptance model, and factors affecting the intention to adopt a cloud-based artificial intelligence platform were analyzed. The results of this study are intended to increase user awareness of cloud-based artificial intelligence platforms and help various industries adopt them through the evaluation framework.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.226-235
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• 2016

The yield of 3D stacked IC manufacturing improves with the pre-bond integrity testing of through silicon vias (TSVs). In this paper, an efficient pre-bond test method is presented based on IEEE std. 1500, which can precisely diagnose any happening of TSV defects. The IEEE std. 1500 wrapper cells are augmented for the proposed method. The pre-bond TSV test can be performed by adjusting the driving strength of TSV drivers and the test clock frequency. The experimental results show the advantages of the proposed approach.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.345-355
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• 2014

Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.

• 오토저널
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• 제14권5호
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• pp.107-116
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• 1992

Recently, it is gradually raised necessity that interface is measured accurately and managed in industrial circle and medical world. An Ultrasonic wave transmitted from a focused beam tranducer is being expected as a powerful tool for NDE of the delamination. The Ultrasonic NDE of the delamination is based on the form of the wave reflected from the interface. In this study results, automatically repeated discrimination analysis method can be devided in the category of all kinds of defects on semiconductor package, and also can be possible to have a sampling of partial delamination.