DOI QR코드

DOI QR Code

Efficient Pre-Bond Testing of TSV Defects Based on IEEE std. 1500 Wrapper Cells

  • Jung, Jihun (Dept. of Computer Science and Engineering, Hanyang University) ;
  • Ansari, Muhammad Adil (Dept. of Computer Science and Engineering, Hanyang University) ;
  • Kim, Dooyoung (Dept. of Computer Science and Engineering, Hanyang University) ;
  • Park, Sungju (Dept. of Computer Science and Engineering, Hanyang University)
  • Received : 2015.06.30
  • Accepted : 2015.11.10
  • Published : 2016.04.30

Abstract

The yield of 3D stacked IC manufacturing improves with the pre-bond integrity testing of through silicon vias (TSVs). In this paper, an efficient pre-bond test method is presented based on IEEE std. 1500, which can precisely diagnose any happening of TSV defects. The IEEE std. 1500 wrapper cells are augmented for the proposed method. The pre-bond TSV test can be performed by adjusting the driving strength of TSV drivers and the test clock frequency. The experimental results show the advantages of the proposed approach.

Keywords

References

  1. K. Chakrabarty, S. Deutsch, H. Thapliyal, and Y. Fangming, "TSV defects and TSV-induced circuit failures: The third dimension in test and design-fortest," in Reliability Physics Symposium (IRPS), 2012 IEEE International, 2012, pp. 5F.1.1-5F.1.12.
  2. C. Po-Yuan, W. Cheng-Wen, and K. Ding-Ming, "On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification," in Asian Test Symposium, 2009. ATS '09., 2009, pp. 450-455.
  3. M. Tsai, A. Klooz, A. Leonard, J. Appel, and P. Franzon, "Through Silicon Via(TSV) defect/ pinhole self test circuit for 3D-IC," in 3D System Integration, 2009. 3DIC 2009. IEEE International Conference on, 2009, pp. 1-8.
  4. S. Deutsch and K. Chakrabarty, "Non-invasive prebond TSV test using ring oscillators and multiple voltage levels," in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013, pp. 1065-1070.
  5. D. Rohde, C. Jager, K. Hazin, and A. Uhlig, "Filling TSV of different dimension using galvanic copper deposition," in Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2011 6th International, 2011, pp. 355-358.
  6. C. Yong-Xiao, H. Yu-Jen, and L. Jin-Fu, "Test cost optimization technique for the pre-bond test of 3D ICs," in VLSI Test Symposium (VTS), 2012 IEEE 30th, 2012, pp. 102-107.
  7. E. J. Marinissen, C. Chun-Chuan, J. Verbree, and M. Konijnenburg, "3D DfT architecture for prebond and post-bond testing," in 3D Systems Integration Conference (3DIC), 2010 IEEE International, 2010, pp. 1-8.
  8. M. Taouil, S. Hamdioui, E. J. Marinissen, and S. Bhawmik, "Impact of mid-bond testing in 3D stacked ICs," in Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on, 2013, pp. 178-183.
  9. M. Taouil, S. Hamdioui, K. Beenakker, and E. J. Marinissen, "Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost," J. Electron. Test., vol. 28, pp. 15-25, 2012. https://doi.org/10.1007/s10836-011-5270-3
  10. H. Ki Jin, M. Swaminathan, and T. Bandyopadhyay, "Electromagnetic Modeling of Through-Silicon Via (TSV) Interconnections Using Cylindrical Modal Basis Functions," Advanced Packaging, IEEE Transactions on, vol. 33, pp. 804-817, 2010. https://doi.org/10.1109/TADVP.2010.2050769
  11. Y. Jhih-Wei, H. Shi-Yu, L. Yu-Hsiang, T. Meng- Hsiu, K. Ding-Ming, C. Yung-Fa, et al., "In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 21, pp. 443-453, 2013. https://doi.org/10.1109/TVLSI.2012.2187543
  12. H. Jin, W. Lingqiu, J. Lifeng, and J. Hao Zheng, "Electrical modeling and characterization of through silicon vias (TSV)," in Microwave and Millimeter Wave Technology (ICMMT), 2012 International Conference on, 2012, pp. 1-4.
  13. G. Katti, M. Stucchi, K. De Meyer, and W. Dehaene, "Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs," Electron Devices, IEEE Transactions on, vol. 57, pp. 256-262, 2010. https://doi.org/10.1109/TED.2009.2034508
  14. N. Yogi, "Implementation of IEEE P1500 Standard for Bidirectional Signals," M.S., Auburn University, 2004.
  15. Y. H. Lin, S. Y. Huang, K. H. Tsai, W. T. Cheng, S. Sunter, Y. F. Chou, et al., "Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 32, pp. 737-747, 2013. https://doi.org/10.1109/TCAD.2012.2236837
  16. H. Li-Ren, H. Shi-Yu, S. Sunter, T. Kun-Han, and C. Wu-Tung, "Oscillation-Based Prebond TSV Test," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 32, pp. 1440-1444, 2013. https://doi.org/10.1109/TCAD.2013.2259626
  17. B. Noia and K. Chakrabarty, "Pre-Bond Probing of Through-Silicon Vias in 3-D Stacked ICs," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 32, pp. 547-558, 2013. https://doi.org/10.1109/TCAD.2012.2226455
  18. "IEEE Standard Testability Method for Embedded Core-Based Integrated Circuits," vol. IEEE Std 1500-2005, ed, 2005, pp. 1-117.
  19. T. McLaurin, "IEEE Std. 1500 Compliant Wrapper Boundary Register Cell," ARM Research and Development, pp. 1-8, Jun. 15 2005.
  20. K. Kim and K. K. Saluja, "Low-Area Wrapper Cell Design for Hierarchical SoC Testing," J. Electron. Test., vol. 25, pp. 347-352, 2009. https://doi.org/10.1007/s10836-009-5117-3
  21. S. K. Goel, E. J. Marinissen, A. Sehgal, and K. Chakrabarty, "Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling," Computers, IEEE Transactions on, vol. 58, pp. 409-423, 2009. https://doi.org/10.1109/TC.2008.169
  22. F. Mirza, T. Raman, M. A. I. Mahmood, S. M. Iqbal, and D. Agonafer, "Parametric thermal analysis of TSVs in a 3-D module based on interconnect delay and silicon efficiency," in Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2012 13th IEEE Intersociety Conference on, 2012, pp. 150-156.
  23. C. Po-Lin, L. Jhih-Wei, and C. Tsin-Yuan, "IEEE Standard 1500 Compatible Delay Test Framework," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 17, pp. 1152-1156, 2009. https://doi.org/10.1109/TVLSI.2009.2013983
  24. E. Beyne, H. Ribot, M. J. Wolf, and F. v. Trapp, "3D TSV Without Limits Webinar," in 3D Incites, 2013.
  25. S. Nassif, K. Bernstein, D. J. Frank, A. Gattiker, W. Haensch, B. L. Ji, et al., "High Performance CMOS Variability in the 65nm Regime and Beyond," in Electron Devices Meeting, 2007. IEDM 2007. IEEE International, 2007, pp. 569-571.
  26. K. Agarwal, F. Liu, C. McDowell, S. Nassif, K. Nowka, M. Palmer, et al., "A test structure for characterizing local device mismatches," in VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on, 2006, pp. 67-68.
  27. J. L. Shin, K. Tam, D. Huang, B. Petrick, H. Pham, H. Changku, et al., "A 40nm 16-core 128-thread CMT SPARC SoC processor," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, 2010, pp. 98-99.
  28. Toshiba Corp. (2015, 20 Oct). Design-for-Test. Available: http://toshiba.semicon-storage.com/apen/product/asic/design-methodologies/design-fortest.html
  29. H. Sung, K. Cho, K. Yoon, and S. Kang, "A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 22, pp. 2380-2387, 2014. https://doi.org/10.1109/TVLSI.2013.2289964
  30. X. Zheng, A. Beece, Z. Dingyou, C. Qianwen, C. Kuan-Neng, K. Rose, et al., "Crosstalk evaluation, suppression and modeling in 3D through-strata-via (TSV) network," in 3D Systems Integration Conference (3DIC), 2010 IEEE International, 2010, pp. 1-8.
  31. C. Jonghyun, S. Eakhwan, Y. Kihyun, P. Jun So, K. Joohee, L. Woojin, et al., "Modeling and Analysis of Through-Silicon Via (TSV) Noise Coupling and Suppression Using a Guard Ring," Components, Packaging and Manufacturing Technology, IEEE Transactions on, vol. 1, pp. 220-233, 2011. https://doi.org/10.1109/TCPMT.2010.2101892