• 마이크로전자및패키징학회지
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• 제18권2호
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• pp.35-41
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• 2011

Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.

• 한국안전학회지
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• 제17권4호
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• pp.94-100
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• 2002

As the use of automatic handling equipment for sensitive semiconductor devices is rapidly increased, manufacturers of electronic components and equipments need to be more alert to the problem of electrostatic discharges(ESD). In order to analyze damage characteristics of semiconductor device damaged by ESD, this study adopts a new charged-device model(CDM), field-induced charged model(FCDM) simulator that is suitable for rapid, routine testing of semiconductor devices and provides a fast and inexpensive test that faithfully represents ESD hazards in plants. High voltage applied to the device under test is raised by the field of non-contacting electrodes in the FCDM simulator, which avoids premature device stressing and permits a faster test cycle. Discharge current and time are measured and calculated. The characteristics of electrostatic attenuation of domestic semiconductor devices are investigated to evaluate the ESD phenomena in the semiconductors. Also, the field charging mechanism, the device thresholds and failure modes are investigated and analyzed. The damaged devices obtained in the simulator are analyzed and evaluated by SEM. The results obtained in this paper can be used to prevent semiconductor devices form ESD hazards and be a foundation of research area and industry relevant to ESD phenomena.

• 우주기술과 응용
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• 제3권4호
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• pp.333-341
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• 2023

본 연구는 국내 100 MeV 양성자가속기와 우주부품시험센터 우주전문시험시설기반을 활용하여 우주부품의 우주 방사선환경 시험검증 기술을 개발하고자 한다. 우주개발의 진전에 따라 고도화된 위성의 임무는 위성의 핵심부품인 메모리 등에 고집적 회로를 필수적으로 사용하고, 태양전지, 광학센서 및 opto-electronics 등 부수 장치에 반도체 소자의 활용이 증가하고 있다. 특히, 전자부품을 우주에 적용하기 위해서는 우주환경 시험을 반드시 거쳐야 하며, 그 중 가장 중요한 것이 고 에너지 방사선환경에서의 우주부품시험이다. 따라서 이에 필요한 우주 방사선 환경 구현 시설을 갖추어 체계적인 시험절차를 수립할 필요가 있다. 한국산업기술시험원 우주부품시험센터는 메모리 부품에 대한 방사선 시험 장치를 제작하고 이를 이용한 메모리 방사선 영향 평가 시험을 수행하였다. 경주양성자가속기에서 100 MeV 양성자를 활용하여 한국에서 활용가능한 수준의 방사선 시험을 진행하였다. 이러한 시험을 통해 메모리 반도체에서 나타나는 single event upset을 관찰할 수 있었다. 향후 해당 시험을 체계화하여 우주산업화에 기반을 마련하고자 한다.

• 한국재료학회지
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• 제1권1호
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• pp.23-28
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• 1991

저압 화학 증착법으로 증착된 다결정실리콘에 As를 이온주입하여 As농도와 $25~105^{\circ}C$ 범위의 측정온도에 따른 비저항의 변화를 조사하였다. 비저항이 최대가 되는 적정 As농도가 존재하였으며 이때 비저항의 온도의존성면에서 활성화에너지 값도 최대를 보였다. Passivation공정후 감소된 비저항이 $O_2$플라즈마 처리와 $N_2$ 분위기에서의 열처리에 의하여 회복되는 현상에 대하여 설명한다.

• 마이크로전자및패키징학회지
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• 제21권4호
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• pp.33-39
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• 2014

To establish the reliability of a packaging structures, adhesion testing of key interfaces is a critical task. Due to the material mismatch, the interface may be prone to delamination failure due to conditions during the manufacturing of the product or just from the day-to-day use. To assess the reliability of the interface adhesion strength testing can be performed during the design phase of the product. One test method of interest is the four-point bending (4PB) adhesion strength test method. This test method has been implemented in a variety of situations to evaluate the adhesion strength of interfaces in bimaterial structures to the interfaces within thin film multilayer stacks. This article presents a review of the 4PB adhesion strength testing method and key implementations of the technique in regards to semiconductor packaging.

• 산업경영시스템학회지
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• 제23권60호
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• pp.73-81
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• 2000

The testing processes for VLSI finished devices are considerably complex because they require different types of ATE to be linked together. Due to the interaction effect between two or more linked ATEs, it is difficult to trace down the cause of the unexpected longer ATE setup time and random yields, which frequently occur in the VLSI circuit-testing laboratory. The goal of this paper is to develop and demonstrate the methodology designed to eliminate the possible interaction factors that might affect the random yields and/or unexpected longer setup time as well as increase the productivity. The statistical method such as design of experiment or multivariate analysis cannot be applied to the final testing floor here directly due to the environmental constraints. Expanded product data information (PDI) is constructed by combining product data information and ATE control information. An architecture utilizing expanded PDI is designed, which enables the engineer to conduct statistical approach investigation and reduce the setup time, as well as increase yield.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.147-155
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• 2017

A new endurance test-pattern generation on NAND-flash memory is proposed to improve test cost. We mainly focus on the correlation between the data-pattern and the device error-rate during endurance testing. The novelty is the development of testing method using quasi-random pattern based on device architectures in order to increase the test efficiency during time-consuming endurance testing. It has been proven by the experiments using the commercial 32 nm NAND flash-memory. Using the proposed method, the error-rate increases up to 18.6% compared to that of the conventional method which uses pseudo-random pattern. Endurance testing time using the proposed quasi-random pattern is faster than that of using the conventional pseudo-random pattern since it is possible to reach the target error rate quickly using the proposed one. Accordingly, the proposed method provides more low-cost testing solutions compared to the previous pseudo-random testing patterns.

• 한국전기전자재료학회논문지
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• 제18권5호
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• pp.431-438
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• 2005

In this paper, we propose the built-in current testing circuit for improving reliability As the integrated CMOS circuits in a chip are increased, the testability on design and fabrication should be considered to reduce the cost of testing and to guarantee the reliability In addition, the high degree of integration makes more failures which are different from conventional static failures and introduced by the short between transistor nodes and the bridging fault. The proposed built-in current testing method is useful for detecting not only these failures but also low current level failures and faster than conventional method. In normal mode, the detecting circuit is turned off to eliminate the degradation of CUT(Circuits Under Testing). The differential input stage in detecting circuit prevents the degradation of CUT in test mode. It is expected that this circuit improves the quality of semiconductor products, the reliability and the testability.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2013년도 춘계학술대회 논문집
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• pp.485-486
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• 2013

• 한국안전학회지
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• 제16권2호
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• pp.57-62
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• 2001

In order to analyze the mechanism of semiconductor device damages by ESD, this paper adopts a new charged-device model(CDM), field-induced charged nudel(FCDM), simulator that is suitable for rapid routine testing of semiconductor devices and provides a fast and inexpensive test that faithfully represents ESD hazards in plants. The high voltage applied to the device under test is raised by the fie]d of non-contacting electrodes in the FCDM simulator. which avoids premature device stressing and permits a faster test cycle. Discharge current md time are measured and calculated The FCDM simulator places the device at a huh voltage without transferring charge to it, by using a non-contacting electrode. The only charge transfer in the FCMD simulator happens during the discharge. This paper examine the field charging mechanism, measure device thresholds, and analyze failure modes. The FCDM simulator provides a Int and inexpensive test that faithfully represents factory ESD hazards. The damaged devices obtained in the simulator are analyzed and evaluated by SEM Also the results in this paper can be used for to prevent semiconductor devices from ESD hazards.