• Journal of the Semiconductor & Display Technology
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• v.18 no.4
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• pp.143-148
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• 2019

Numerous pipe lines can be found on various plant-based industrial sites. These pipelines should be periodically checked for defects. Most of these pipelines are internally inaccessible and difficult to visually inspect. Therefore, the inspection is being carried out with the help of non-contact inspection equipment such as ultrasonic flaw detection equipment. The use of ultrasonic flaw detection equipment can raise time and efficiency issues. In order to solve this problem, we will study the basic technology necessary for the development of automated inspection system equipped with ultrasonic measuring equipment and verify the validity through the fabrication of the demonstration device.

• Journal of the Semiconductor & Display Technology
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• v.19 no.4
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• pp.126-129
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• 2020

We introduce a lifetime assessment technique using deep learning algorithm with complex electrical parameters such as resistivity, permittivity, impedance parameters as integrated indicators for predicting the degradation of the organic molecules. The evaluation system consists of fully automated in-situ measurement system and multiple layer perceptron learning system with five hidden layers and 1011 perceptra in each layer. Prediction accuracies are calculated and compared depending on the physical feature, learning hyperparameters. 62.5% of full time-series data are used for training and its prediction accuracy is estimated as r-square value of 0.99. Remaining 37.5% of the data are used for testing with prediction accuracy of 0.95. With k-fold cross-validation, the stability to the instantaneous changes in the measured data is also improved.

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.49-53
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• 2023

In this paper, we propose an antirandom pattern-based test method considering power consumption to compensate for the problem that the fault coverage through random test decreases or the test time increases significantly when the DUT circuit structure is complex or large. In the proposed method, a group unit test pattern generation process and rearrangement process are added to improve the problems of long calculation time and high-power consumption, which are disadvantages of the previous antirandom test.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.23-26
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• 2022

In this paper, our ray tracing hardware is implemented on the latest high-capacity FPGA board. The system included ray tracing hardware for rendering and tree building hardware for handling dynamic scenes. The FPGA board used in the implementation is a Xilinx Alveo U250 accelerator card for data centers. This included 12 ray tracing hardware cores and 1 tree-building hardware core. As a result of testing in various scenes in Full HD resolution, the FPS performance of the proposed ray tracing system was measured from 8 to 28. The overall average is about 17.7 FPS.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.136-141
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• 2023

Artificial intelligence is becoming a global hot topic and is being actively applied in various industrial fields. Not only is artificial intelligence being applied to industrial sites in an on-premises method, but cloud-based artificial intelligence platforms are expanding into "as a service" type. The purpose of this study is to develop and verify a measurement tool for an evaluation framework for the adoption of a cloud-based artificial intelligence platform and test the interrelationships of evaluation variables. To achieve this purpose, empirical testing was conducted to verify the hypothesis using an expanded technology acceptance model, and factors affecting the intention to adopt a cloud-based artificial intelligence platform were analyzed. The results of this study are intended to increase user awareness of cloud-based artificial intelligence platforms and help various industries adopt them through the evaluation framework.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.226-235
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• 2016

The yield of 3D stacked IC manufacturing improves with the pre-bond integrity testing of through silicon vias (TSVs). In this paper, an efficient pre-bond test method is presented based on IEEE std. 1500, which can precisely diagnose any happening of TSV defects. The IEEE std. 1500 wrapper cells are augmented for the proposed method. The pre-bond TSV test can be performed by adjusting the driving strength of TSV drivers and the test clock frequency. The experimental results show the advantages of the proposed approach.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.345-355
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• 2014

Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.

• Journal of the korean Society of Automotive Engineers
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• v.14 no.5
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• pp.107-116
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• 1992

Recently, it is gradually raised necessity that interface is measured accurately and managed in industrial circle and medical world. An Ultrasonic wave transmitted from a focused beam tranducer is being expected as a powerful tool for NDE of the delamination. The Ultrasonic NDE of the delamination is based on the form of the wave reflected from the interface. In this study results, automatically repeated discrimination analysis method can be devided in the category of all kinds of defects on semiconductor package, and also can be possible to have a sampling of partial delamination.

• Proceedings of the Korea Society for Simulation Conference
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• 2002.05a
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• pp.145-149
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• 2002

92∼3년 A 라인에서 처음으로 Bay 내에 Conveyor (Intra) 사용한 Stocker to Equipment에서 Material(Lot) Moving을 위한 Project를 실시하였으나 예상과는 달리 Conveyor Capability가 부족하여 장비에서 Rundown 현상이 발생하였다. 정상적인 Simulation없이 Design한 Conveyor System은 막대한 금전투자, 인력투자, 설치Testing 철거 등으로 인한 라인 작업방해 등 막대한 손실을 남기는 실패를 가져왔다. 본 연구에서는 이미 장비가 Setup되어 Running중에 있는 반도체 라인 환경 또는 신규로 새로운 라인을 Design할 때 사람을 대신하여 Bay내에서 Lot을 Stocker에서 장비 또는 장비에서 장비로 이동을 Conveyer를 사용할 경우 적정 Conveyor Capability를 산정 하는데 그 목적이 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.213-223
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• 2013

A unified channel thermal noise model valid in all operation regions is presented for short channel MOS transistors. It is based on smooth interpolation between weak and strong inversion models and consistent physical model including velocity saturation, channel length modulation, and carrier heating. From testing for noise benchmark and comparing with published noise data, it is shown that the proposed noise model could be useful in simulating the MOSFET channel thermal noise in all operation regions.