• 제목/요약/키워드: Semiconductor Process

검색결과 2,809건 처리시간 0.04초

Deformation of the AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistor characteristics by UV irradiation

  • Lim, Jin Hong;Kim, Jeong Jin;Yang, Jeon Wook
    • 전기전자학회논문지
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    • 제17권4호
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    • pp.531-536
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    • 2013
  • The impact of UV irradiation process on the AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistor was investigated. Due to the high intensity UV irradiation before the gate dielectric deposition, the conductivity of AlGaN/GaN structure and the drain saturation current of the transistor increased by about 10 %. However, the pinch off characteristics of transistor was severely deformed by the process. By comparing the electrical characteristics of the transistors, it was proposed that the high intensity UV irradiation formed a sub-channel under the two dimensional electron gas of AlGaN/GaN structure even without additional impurity injection.

Fault Detection in the Semiconductor Etch Process Using the Seasonal Autoregressive Integrated Moving Average Modeling

  • Arshad, Muhammad Zeeshan;Nawaz, Javeria Muhammad;Hong, Sang Jeen
    • Journal of Information Processing Systems
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    • 제10권3호
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    • pp.429-442
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    • 2014
  • In this paper, we investigated the use of seasonal autoregressive integrated moving average (SARIMA) time series models for fault detection in semiconductor etch equipment data. The derivative dynamic time warping algorithm was employed for the synchronization of data. The models were generated using a set of data from healthy runs, and the established models were compared with the experimental runs to find the faulty runs. It has been shown that the SARIMA modeling for this data can detect faults in the etch tool data from the semiconductor industry with an accuracy of 80% and 90% using the parameter-wise error computation and the step-wise error computation, respectively. We found that SARIMA is useful to detect incipient faults in semiconductor fabrication.

화합물반도체공장의 생산정보수집시스템 (Data Acquisition System of Compound Semiconductor Fabrication)

  • 이승우;송준엽;이화기
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2006년도 춘계학술대회 논문집
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    • pp.335-336
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    • 2006
  • Compound semiconductor manufacturing environment also has been emerged as mass customization and open foundry service so integrated manufacturing system is needed. In this study, we design data acquisition system of compound semiconductor fabrication that has monitoring and control of process. The developed DAS is consisted of key-in system inputted by operator and automatic acquisition system by GEM protocol. And we implemented them in the actual compound semiconductor. It is expected that using developed system would offer precise process information to buyer, reduce a lead-time, and obey a due-dates and so on.

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반도체용 PCB 기판시스템의 구조해석 (Structural Analysis of a PCB Substrate System for Semiconductor)

  • 임경화;양손;윤종국;김영균;유선중
    • 반도체디스플레이기술학회지
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    • 제10권4호
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    • pp.113-118
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    • 2011
  • According to the high accuracy of semiconductor equipments, PCB substrate with much thin thickness is required. However, it is very difficult to sustain the PCB substrate without deformation in case of horizontal installation, due to low bending stiffness. In this research, new PCB process equipment with vertical installation has been developed in order to solve the problem of PCB substrate damage during etching process. As the main parts of etching system on PCB substrate, PCB substrate and JIG are analyzed through finite element method and experimental test. Through the analysis results of stress state, we could find the optimal JIG design to make the damage as low as possible.

극자외선 리소그라피에서의 Sub-resolution assist feature를 이용한 근접효과보정 (Optical Proximity Correction using Sub-resolution Assist Feature in Extreme Ultraviolet Lithography)

  • 김정식;홍성철;장용주;안진호
    • 반도체디스플레이기술학회지
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    • 제15권3호
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    • pp.1-5
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    • 2016
  • In order to apply sub-resolution assist feature (SRAF) in extreme ultraviolet lithography, the maximum non-printing SRAF width and lithography process margin needs to be improved. Through simulation, we confirmed that the maximum SRAF width of 6% attenuated phase shift mask (PSM) is large compared to conventional binary intensity mask. The increase in SRAF width is due to dark region's reflectivity of PSM which consequently improves the process window. Furthermore, the critical dimension error caused by variation of SRAF width and center position is reduced by lower change in diffraction amplitude. Therefore, we speculate that the margin of SRAF application will be improved by using PSM.

Particle 입자에 의한 CMP 마이크로 스크래치 발생 규명 (Particle induced micro-scratch in CMP process)

  • 황응림;김형환;이훈;피승호;최봉호
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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    • pp.40-41
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    • 2005
  • In this study, we proposed CMP micro-scratches generated by contaminative particle which existed on the wafer surface prior to CMP process. The CMP micro-scratches are one of the slurry abrasive related damage. To reduce the micro-scratches, research efforts have been devoted to the optimization of slurry abrasive size distribution. In addition of slurry abrasive, it was found that contaminative particles also were major CMP micro-scratch source.

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Wafer Packing Box 안정화 설계 (Design Alterations of a Packing Box for the Semiconductor Wafer to Improve Stability)

  • 윤재훈;허장욱;이일환
    • 반도체디스플레이기술학회지
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    • 제21권1호
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    • pp.62-66
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    • 2022
  • Semiconductor is one of the most internationally competitive areas among domestic industries, the major concern of which is the stability of the wafer manufacturing processes. The packaging process is the final step in wafer manufacturing. Problems in the wafer packaging process cause large losses. The vibrations are supposed to be the most important factors for the packaging quality. In this study, the structure of a packaging box was analyzed through experiments and computer simulations, and further the effects of design alterations to suppress the vibrations have been investigated. The final result shows that the vibrations can be reduced substantially to improve the stability of the structure.

반도체 공정 교육을 위한 교육용 컴퓨터 모델 설계 및 구현 (The Design and Implementation of an Educational Computer Model for Semiconductor Manufacturing Courses)

  • 한영신;전동훈
    • 한국시뮬레이션학회논문지
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    • 제18권4호
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    • pp.219-225
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    • 2009
  • 본 연구는 복잡하고 다양한 반도체 웨이퍼 가공(FAB) 공정의 전체적인 흐름을 컴퓨터 모델로 구축하고 이를 Device 단면도를 나타내는 프리젠테이션 툴과 연동시키는 교육 모델의 개발을 목적으로 하였다. 급변하는 세계 반도체 시장에서 국내 반도체 업체는 지속적인 기술 개발과 더불어 효율적인 생산관리에 대응할 수 있도록 하여 국제 경쟁력을 키워야 할 것이다. 따라서 본 연구에서 다루어진 공정의 흐름과 각 단위공정의 특성을 바탕으로 설립된 모델은 서울대학교 반도체 공동 연구소를 대상으로 구현되었으나 앞으로 생산 관리를 담당할 국내 반도체 업체들의 신입사원과 현장기술자의 질적 향상을 위한 시청각 교육용 자료로의 활용 시 상당한 효과를 거둘 것이라 예상된다. 이는 생산업체에 국한되어지는 것만은 아니며 반도체 공정에 관련된 대학 학과목에서도 활용되어지리라 생각된다. 또한 확장성과변화에 유연한 모델을 개발함으로써 반도체 생산 업체들은 구성된 표준 모델을 이용하여 각 회사의 실정에 맞추어 자사에 대한 시뮬레이션을 손쉽게 수행함으로써 많은 교육 효과와 이에 따른 원가 절감의 효과까지 거둘 수 있을 것이다.

Interval Scan Inspection Technique for Contact Failure of Advanced DRAM Process using Electron Beam-Inspection System

  • Oh, J.H.;Kwon, G.;Mun, D.Y.;Kim, D.J.;Han, I.K.;Yoo, H.W.;Jo, J.C.;Ominami, Y.;Ninomiya, T.;Nozoe, M.
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제12권1호
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    • pp.34-40
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    • 2012
  • We have developed a highly sensitive inspection technique based on an electron beam inspection for detecting the contact failure of a poly-Si plugged layer. It was difficult to distinguish the contact failure from normal landing plugs with high impedance. Normally, the thermal annealing method has been used to decrease the impedance of poly-Si plugs and this method increases the difference of charged characteristics and voltage contrast. However, the additional process made the loss of time and broke down the device characteristics. Here, the interval scanning method without thermal annealing was effectively applied to enhance the difference of surface voltage between well-contacted poly-Si plugs and incomplete contact plugs. It is extremely useful to detect the contact failures of non-annealed plug contacts with high impedance.