• 제어로봇시스템학회논문지
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• 제21권9호
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• pp.875-880
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• 2015

Traditional semiconductor process control has been performed through statistical process control techniques in a constant process-recipe conditions. However, the complexity of the interior of the etching apparatus plasma physics, quantitative modeling of process conditions due to the many difficult features constraints apply simple SISO control scheme. The introduction of the Advanced Process Control (APC) as a way to overcome the limits has been using the APC process control methodology run-to-run, wafer-to-wafer, or the yield of the semiconductor manufacturing process to the real-time process control, performance, it is possible to improve production. In addition, it is possible to establish a hierarchical structure of the process control made by the process control unit and associated algorithms and etching apparatus, the process unit, the overall process. In this study, the research focused on the methodology and monitoring improvements in performance needed to consider the process management of future developments in the semiconductor manufacturing process in accordance with the age of the APC analysis in real applications of the semiconductor manufacturing process and process fault diagnosis and control techniques in progress.

• 대한안전경영과학회지
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• 제17권3호
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• pp.355-362
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• 2015

There has been an increase of using Bosch Process to fabricate MEMS Device, TSV, Power chip for straight etching profile. Essentially, the interest of TSV technology is rapidly floated, accordingly the demand of Bosch Process is able to hold the prominent position for straight etching of Si or another wafers. Recently, the process to prevent under etching or over etching using EPD equipment is widely used for improvement of mechanical, electrical properties of devices. As an EPD device, the OES is widely used to find accurate end point of etching. However, it is difficult to maintain the light source from view port of chamber because of contamination caused by ion conflict and byproducts in the chamber. In this study, we adapted the SPOES to avoid lose of signal and detect less open ratio under 1 %. We use 12inch Si wafer and execute the through etching 500um of thickness. Furthermore, to get the clear EPD data, we developed an algorithm to only receive the etching part without deposition part. The results showed possible to find End Point of under 1 % of open ratio etching process.

• 반도체디스플레이기술학회지
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• 제23권2호
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• pp.6-11
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• 2024

This paper presents the design and experimental analysis of a cryogenic refrigeration system for -100 ℃, primarily intended for semiconductor etching process. The refrigeration system utilizes non-flammable mixed refrigerant Joule-Thomson refrigeration cycle, incorporating a precooling stage to enhance overall performance. The selected refrigerants for the system include R1234yf for the precooling stage, and Ar, R14, R23 and R218 for the main cooling stage of the Joule-Thomson refrigeration cycle. Design results according to the system constraints and experimental results are discussed, including lowest evaporation temperature, compressor isentropic efficiency and overall pressure tendencies. The achieved refrigerant fraction from optimal design is Ar: R14: R23: R218 = 0.15: 0.4: 0.15: 0.3, indicating COP of 0.1118 at the isentropic compressor efficiency of 50%. The experimental result shows the developed system reaches steady state in approximately 3 hours.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2002년도 제23회 학술발표회 초록집
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• pp.172-173
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• 2002

• 한국표면공학회지
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• 제48권6호
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• pp.360-370
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• 2015

As the size of the semiconductor devices shrinks to nanometer scale, the importance of plasma etching process to the fabrication of nanometer scale semiconductor devices is increasing further and further. But for the nanoscale devices, conventional plasma etching technique is extremely difficult to meet the requirement of the device fabrication, therefore, other etching techniques such as use of multi frequency plasma, source/bias/gas pulsing, etc. are investigated to meet the etching target. Until today, various pulsing techniques including pulsed plasma source and/or pulse-biased plasma etching have been tested on various materials. In this review, the experimental/theoretical studies of pulsed plasmas during the nanoscale plasma etching on etch profile, etch selectivity, uniformity, etc. have been summarized. Especially, the researches of pulsed plasma on the etching of silicon, $SiO_2$, and magnetic materials in the semiconductor industry for further device scaling have been discussed. Those results demonstrated the importance of pulse plasma on the pattern control for achieving the best performance. Although some of the pulsing mechanism is not well established, it is believed that this review will give a certain understanding on the pulsed plasma techniques.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.26-31
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• 2023

We investigated the impact of NF₃ / H₂O remote plasma dry cleaning conditions on the SiO₂ etching rate at different preparation states during the fabrication of ultra-large-scale integration (ULSI) devices. This included consideration of factors like Si crystal orientation prior to oxidation and three-dimensional structures. The dry cleaning process were carried out varying the parameters of pressure, NF₃ flow rate, and H₂O flow rate. We found that the pressure had an effective role in controlling anisotropic etching when a thin SiO₂ layer was situated between Si₃N₄ and Si layers in a multilayer trench structure. Based on these observations, we would like to provide further guidelines for implementing the dry cleaning process in the fabrication of semiconductor devices having 3D structures.

• 반도체디스플레이기술학회지
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• 제21권3호
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• pp.74-79
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• 2022

In this study, the plasma corrosion resistance and the change in the number of contamination particles generated using the plasma etching process and cleaning process of coating parts for semiconductor plasma etching equipment were investigated. As the coating method, atmospheric plasma spray (APS) was used, and the powder materials were Y₂O₃ and Y₃Al₅O₁₂ (YAG). There was a clear difference in the densities of the coatings due to the difference in solubility due to the melting point of the powdered material. As a plasma environment, a mixed gas of CF₄, O₂, and Ar was used, and the etching process was performed at 200 W for 60 min. After the plasma etching process, a fluorinated film was formed on the surface, and it was confirmed that the plasma resistance was lowered and contaminant particles were generated. We performed a surface cleaning process using piranha solution(H₂SO₄(3):H₂O₂(1)) to remove the defect-causing surface fluorinated film. APS-Y₂O₃ and APS-YAG coatings commonly increased the number of defects (pores, cracks) on the coating surface by plasma etching and cleaning processes. As a result, it was confirmed that the generation of contamination particles increased and the breakdown voltage decreased. In particular, in the case of APS-YAG under the same cleaning process conditions, some of the fluorinated film remained and surface defects increased, which accelerated the increase in the number of contamination particles after cleaning. These results suggest that contaminating particles and the breakdown voltage that causes defects in semiconductor devices can be controlled through the optimization of the APS coating process and cleaning process.

• 반도체디스플레이기술학회지
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• 제13권2호
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• pp.29-35
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• 2014

In this study general solar cell production process was complemented, with research on improvement of solar cell efficiency through surface structure and thermal annealing process. Firstly, to form the pyramid structure, the saw damage removal (SDR) processed surface was undergone texturing process with reactive ion etching (RIE). Then, for the formation of smooth pyramid structure to facilitate uniform doping and electrode formation, the surface was etched with HND(HF : HNO3 : D.I. water=5 : 100 : 100) solution. Notably, due to uniform doping the leakage current decreased greatly. Also, for the enhancement and maintenance of minority carrier lifetime, antireflection coating thermal annealing was done. To maintain this increased lifetime, front electrode was formed through Au plating process without high temperature firing process. Through these changes in two processes, the leakage current effect could be decreased and furthermore, the conversion efficiency could be increased. Therefore, compared to the general solar cell with a conversion efficiency of 15.89%, production of high efficiency solar cell with a conversion efficiency of 17.24% was made possible.

• 대한안전경영과학회지
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• 제23권3호
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• pp.27-33
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• 2021

The purpose of this study is to present a novel indicator for analyzing machine failure based on its idle time and productivity. Existing machine repair plan was limited to machine experts from its manufacturing industries. This study evaluates the repair status of machines and extracts machines that need improvement. In this study, F-RPN was calculated using the etching process data provided by the 2018 PHM Data Challenge. Each S(S: Severity), O(O: Occurence), D(D: Detection) is divided into the idle time of the machine, the number of fault data, and the failure rate, respectively. The repair status of machine is quantified through the F-RPN calculated by multiplying S, O, and D. This study conducts a case study of machine in a semiconductor etching process. The process capability index has the disadvantage of not being able to divide the values outside the range. The performance of this index declines when the manufacturing process is under control, hereby introducing F-RPN to evaluate machine status that are difficult to distinguish by process capability index.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2006년도 춘계학술대회
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• pp.198-201
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• 2006

To produce fine structure with uniform surface of barrier ribs in PDP, acid etching process has been used in manufacture process. It is necessary to understand the mechanism of etching, particularly on the interface of ceramic fillers and matrix glass. We investigated the effect of ceramic fillers (ZnO, $Al_{2}O_3$) on the microstructure of borate glass system to find an etching mechanism of barrier ribs. The harrier ribs was etched with a several steps, dissolving a small amount of residual glass, taking out alumina fillers, and removing a cluster type of ZnO fillers and glass matrix.