• Journal of Mechanical Science and Technology
• /
• v.19 no.4
• /
• pp.968-975
• /
• 2005

The shearing process for the sheet metal is normally used in the precision elements such as semi-conductor components. In these precision elements, the burr formation brings a bad effect on the system assembly and demands the additional de-burring process, so this imposes high cost on manufacturing. In this paper, we have developed the in-situ auto-aligning precision meso-punching system to investigate the burr formation mechanism and ultimately minimize burr. Firstly, we introduced the punch-die contact sensing method to align the punch and the die at initial state prior to the punching process. Secondly, by using the low-price semi-con­ductor laser, burr formed on the edges is measured intermittently during the punching process. We could, finally, make burr on the sheet metal uniformized and minimized by controlling of the precision X - Y table, $1\;{\mu}m$ resolution, and measuring burr height by semiconductor laser. Experimental results show the validity of our system for pursuing the burr-free punched elements.

• Design & Manufacturing
• /
• v.14 no.1
• /
• pp.36-41
• /
• 2020

Recently, due to the development of MEMS technology, researches for the production of effective micro structures and shapes have been actively conducted. However, the process technology based on chemical etching has a number of problems such as environmental pollution and time problems due to multi-process. Various processes to cope with this process are being studied, and one of the mechanical etching processes is the powder blasting process. This process is a method of spraying fine particles, which has the advantage of being an effective process in manufacturing hard brittle materials. However, it is also a process that adversely affects the material surface roughness and material properties due to the impact of the injection of fine particles. In this study, after fabricating micro-channels in fused silica glass with excellent optical properties among the hard brittle materials, we used the nano indentation system to analyze the micro parts using nano-particles as well as machinability and surface roughness analysis of the processed surface. The analysis was performed for the effective processing of powder blasting.

• Journal of Welding and Joining
• /
• v.32 no.3
• /
• pp.11-18
• /
• 2014

TSV(through silicon via) filling technology is making a hole in Si wafer and electrically connecting technique between front and back of Si die by filling with conductive metal. This technology allows that a three-dimensionally connected Si die can make without a large number of wire-bonding. These TSV technologies require various engineering skills such as forming a via hole, forming a functional thin film, filling a conductive metal, polishing a wafer, chip stacking and TSV reliability analysis. This paper addresses the TSV filling using Cu electrodeposition. The impact of plating conditions with additives and current density on electrodeposition will be considered. There are additives such as accelerator, inhibitor, leveler, etc. suitably controlling the amount of the additive is important. Also, in order to fill conductive material in whole TSV hole, current wave forms such as PR(pulse reverse), PPR(periodic pulse reverse) are used. This study about semiconductor packaging will be able to contribute to the commercialization of 3D TSV technology.

• Journal of the Microelectronics and Packaging Society
• /
• v.14 no.1
• /
• pp.19-26
• /
• 2007

This study was focused on the feasibility of ultrasonic bonding of Au flip chip bumps for a practical complementary metal oxide semiconductor (CMOS) image sensor with electroplated Au substrate. The ultrasonic bonding was carried out with different bonding pressures and times after the atmospheric pressure plasma cleaning, and then the die shear test was performed to optimize the ultrasonic bonding parameters. The bonding pressure and time strongly affected the bonding strength of the bumps. The Au flip chip bumps were successfully bonded with the electroplated Au substrate at room temperature, and the bonding strength reached approximate 73 MPa under the optimum conditions.

• ETRI Journal
• /
• v.36 no.6
• /
• pp.931-941
• /
• 2014

Many methodologies for clock mesh networks have been introduced for two-dimensional integrated circuit clock distribution networks, such as methods to reduce the total wirelength for power consumption and to reduce the clock skew variation through consideration of buffer placement and sizing. In this paper, we present a methodology for clock mesh to reduce both the clock skew and the total wirelength in three-dimensional integrated circuits. To reduce the total wirelength, we construct a smaller mesh size on a die where the clock source is not directly connected. We also insert through-silicon vias (TSVs) to distribute the clock signal using an effective clock TSV insertion algorithm, which can reduce the total wirelength on each die. The results of our proposed methods show that the total wirelength was reduced by 12.2%, the clock skew by 16.11%, and the clock skew variation by 11.74%, on average. These advantages are possible through increasing the buffer area by 2.49% on the benchmark circuits.

• Design & Manufacturing
• /
• v.10 no.2
• /
• pp.50-54
• /
• 2016

In the semiconductor industry the final products were checked for several environments before sell the products. The burning test of memory and chip was implemented in reliability for all of parts. The memory and chip were developed to high density memory and high performance chip, so circuit design was also high integrated and the test bed was needed to be thin and fine pitch socket. LGA(Land Grid Array) IC socket with thin wall thickness was designed to satisfy this requirement. The LGA IC socket plastic part was manufacture by injection molding process, it was needed accuracy, stiffness and suit resin with high flowability. In this study, injection molding process analysis was executed for 2 and 4 cavities moldings with runner, gate and sprue. The warpage analysis was also implemented for further gate removal process. Through the analyses the total deformations of the moldings were predicted within maximum 0.05mm deformation. Finally in consideration of these results, 2 and 4 cavities molds were designed and made and tested in injection molding process.

• Journal of the Korean Society for Precision Engineering
• /
• v.11 no.1
• /
• pp.150-156
• /
• 1994

To meet the process requirement of semiconductor device manufacturing, it is necessary to improve the alignment accuracy in exposure equipments. We developed the excimer laser stepper and will describe the methodology for alignment measurement and experimental results. Our wafer alignment system consists of off-axis optics, TTL(Through The Lens) optics and high precision stage. Off-axis alignment utilizes the image processing and /or diffraction from thealign marks of off-centered chip area. On the other hand, TTL alignment can be used for the die-by-die alignment using dual beam interferometry. When only off-axis alignment was used, the experimental alignment error(lml+3 .sigma. ) was 0.26-0.29 .mu. m, and will be reduced down to 0.15 .mu. m by adding TTL alignment.

• Design & Manufacturing
• /
• v.7 no.1
• /
• pp.55-59
• /
• 2013

A Light Emitting Diode(LED) is a semiconductor device which converts electricity into light. LEDs are widely used in a field of illumination, LCD(Liquid Crystal Display) backlight, mobile signals because they have several merits, such as low power consumption, long lifetime, high brightness, fast response, environment friendly. In general, LEDs production does die bonding and wire bonding on board, and do silicon and phosphor dispensing to protect LED chip and improve brightness. Then lens molding process is performed using mixed liquid silicon rubber(LSR) by resin and hardener. A mixture of resin and hardener affect the optical characteristics of the LED lens. In this paper, computational design of static mixer was performed for mixing of liquid silicon. To evaluate characteristic of mixing efficiency, finite element model of static mixer was generated, and fluidic analysis was performed according to length of mixing element. Finally, optimal condition of length of mixing element was applied to static mixer from result of fluidic analysis.

• Journal of the Microelectronics and Packaging Society
• /
• v.20 no.3
• /
• pp.31-35
• /
• 2013

TSOP(Thin Small Outline Package) is the IC package using lead frame, which is the type of low cost package for white electronics, auto mobile, desktop PC, and so on. Its performance is not excellent compared to BGA or flip-chip CSP, but it has been used mostly because of low price of TSOP package. However, it has been issued in TSOP package that thermal deflection of lead frame occurs frequently during molding process and Au wire between semiconductor die and pad is debonded. It has been required to solve this problem through substituting materials with low CTE and improving structure of lead frame. We focused on developing the lead frame structure having thermal stability, which was carried out by numerical analysis in this study. Thermal deflection of lead frame in TSOP package was simulated with positions of anti-deflection adhesives, which was ranging 198 um~366 um from semiconductor die. It was definitely understood that thermal deflection of TSOP package with anti-deflection adhesives was improved as 30.738 um in the case of inside(198 um), which was compared to that of the conventional TSOP package. This result is caused by that the anti-deflection adhesives is contributed to restrict thermal expansion of lead frame. Therefore, it is expected that the anti-deflection adhesives can be applied to lead frame packages and enhance their thermal deflection without any change of substitutive materials with low CTE.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.1
• /
• pp.122-130
• /
• 2015

This paper presents a 6 Gb/s 4-channel arrayed transimpedance amplifiers (TIA) with the gain control for 4-channel passive optical network in $0.13{\mu}m$ complementary metal oxide semiconductor (CMOS) technology. A regulated cascode input stage and inductive-series peaking are proposed in order to increase the bandwidth. Also, a variable gain control is implemented to provide flexibility to the overall system. The TIA has a maximum $98.1dB{\Omega}$ gain and an input current noise level of about 37.8 pA/Hz. The die area of the fabricated TIA is $1.9mm{\times}2.2mm$ for 4-channel. The power dissipation is 47.64 mW/1ch.