• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.445-448
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• 2006

Bias stress effect in pentacene organic thin-flim transistors with cross-linked PVA gate dielectric is analyzed. For negative gate bias stress, positive threshold voltage shift is observed. The injected charges from the gate electrode to the defect states of gate dielectric are regarded as the main origin of $V_T$ shift. The reduced bias stress effect using $SiO_2$ blocking layer confirms the assumed mechanism. It is also demonstrated that the inverter with $SiO_2$ blocking layer shows the negligible hysteresis owing to the reduced bias stress effect.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.128.1-128.1
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• 2016

Nitrided-metal gates on the high-${\kappa}$ dielectric material are widely studied because of their use for sub-20nm semiconductor devices and the academic interest for the evanescent states at the Si/insulator interface. Issues in these systems with the Si substrate are the electron mobility degradation and the reliability problems caused from N defects that permeates between the Si and the $SiO_2$ buffer layer interface from the nitrided-gate during the gate deposition process. Previous studies proposed the N defect structures with the gap states at the Si band gap region. However, recent experimental data shows the possibility of the most stable structure without any N defect state between the bulk Si valence band maximum (VBM) and conduction band minimum (CBM). In this talk, we present a new type of the N defect structure and the electronic structure of the proposed structure by using the first-principles calculation. We find that the pair structure of N atoms at the $Si/SiO_2$ interface has the lowest energy among the structures considered. In the electronic structure, the N pair changes the eigenvalue of the silicon-induced gap state (SIGS) that is spatially localized at the interface and energetically located just above the bulk VBM. With increase of the number of N defects, the SIGS gradually disappears in the bulk Si gap region, as a result, the system gap is increased by the N defect. We find that the SIGS shift with the N defect mainly originates from the change of the kinetic energy part of the eigenstate by the reduction of the SIGS modulation for the incorporated N defect.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.266-276
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• 2001

Due to the rapid development of semiconductor technology, the complexity of VLSI circuits has heavily increased. With the increased densities of integrated circuits, several different types of faults can occur Thus, testing such circuits is becoming a sever problem. Delay testing can detect system timing failures caused by delay faults. However, the conventional delay fault coverage in terms of the number of detected faults may not be an effective measure of delay testing because, unlike a stuck-at-faults, the impact of a delay fault is dependent on its delay defect size rather than on its existence. Thus, the effectiveness of delay testing is dependent on the propagation delay of the path to be tested, the delay defect size, and the system clock interval. This paper proposes a new delay defect fault coverage that considers both propagation delay of the path to be tested and additional delay defect size. And the relationship between delay defect fault coverage and defect level is analyzed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.05b
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• pp.17-21
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• 2001

We proposed that concentrations of cartier electron as well as ionized donor defects in nonstoichiometric ZnO are proportional to $P^{-1/2}_{O_2}$, whenever they ionizes singly or doubly, by employing the Fermi-Dirac (FD) statistics for ionization of the native thermal defects $Zn_i$ and $V_o$. The effect of acceptor defect, zinc vacancy $V_{Zn}$made by the Frenkel and Schottky disorder reactions, on carrier concentrations was discussed. By application of the FD statistics law to their ionization while the formation of defects is assumed governed by the mass-action law, the calculation results indicate; 1. ZnO shows n-type conductivity with $N_D>$N_A$ and majority concentration of $n{\propto}\;P^{-1/2}_{O_2}$ in a range of $P_{O_2}$, lower than a critical value. 2. As the concentration of acceptor $V_{Zn}$ increases proportional to $P^{1/2}_{O_{2}}$, ZnO made at extremely high $P_{O_{2}}$, can have p-type conductivity with majority concentration of p ${\propto}\;P^{-1/2}_{O_{2}}$. One may not, however, obtain p-type ZnO if the pressure for $N_{D}<$N_{A}$ is too high.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.17 no.5
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• pp.192-195
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• 2007

Structural and electronic properties of bulk GaN with nitrogen vacancy($V_N$), oxygen substitution on nitrogen site($O_N$), and complex of nitrogen vacancy and oxygen substitution on nitrogen site($V_N-O_N$) were investigated using the first principle calculations. It was found that stability of defect formation is dependent on the epilayer growth conditions. The complex of $V_N-O_N$ is energetically the most favorable state in a condition of Ga-rich, however, oxygen substitution in nitrogen site is the most favorable state in N-rich condition. The electronic property of complex with negative charge states at $\Gamma$ point was changed from semiconductor to metal. On the contrary, the properties of nitrogen vacancy except for neutral charge state have shown the semiconductor characteristics at $\Gamma$ point. In the oxygen substitution on nitrogen site, the energy differences between conduction band minimum and Fermi level were smaller than that of defect-free GaN.

• Journal of the Semiconductor & Display Technology
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• v.15 no.3
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• pp.18-23
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• 2016

QFN (Quad Flat No-leads Package) is one of the SMD (Surface Mount Device). Since there is no lead in QFN, there are many defects on solder. Therefore, we propose an efficient mechanism for QFN solder defect detection at this paper. For this, we employ Convolutional Neural Network (CNN) of the Machine Learning algorithm. QFN solder's color multi-layer images are used to train CNN. Since these images are 3-channel color images, they have a problem with applying to CNN. To solve this problem, we used each 1-channel grayscale image (Red, Green, Blue) that was separated from 3-channel color images. We were able to detect QFN solder defects by using this CNN. In this paper, it is shown that the CNN is superior to the conventional multi-layer neural networks in detecting QFN solder defects. Later, further research is needed to detect other QFN.

• Journal of Korean Institute of Industrial Engineers
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• v.41 no.6
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• pp.579-587
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• 2015

Semiconductor manufacturing industry is a high density integration industry because it generates a vest number of data that takes about 300~400 processes that is supervised by numerous production parameters. It is asked of engineers to understand the correlation between different stages of the manufacturing process which is crucial in reducing production costs. With complex manufacturing processes, and defect processing time being the main cause. In the past, it was possible to grasp the corelation among manufacturing process stages through the engineer's domain knowledge. However, It is impossible to understand the corelation among manufacturing processes nowadays due to high density integration in current semiconductor manufacturing. in this paper we propose a canonical correlation analysis (CCA) using both wafer test voltage variables and fail bit counts variables. using the method we suggested, we can increase the semiconductor yield which is the result of the package test.

• Journal of the Semiconductor & Display Technology
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• v.15 no.3
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• pp.35-39
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• 2016

Extreme Ultraviolet Lithography (EUVL) is the most promising technique in the field of Next Generation Lithography (NGL) expected to be used in the 1x-nm node for High Volume Manufacturing (HVM). But there exits remaining challenges for proper defect control of EUV mask. It was considered development of EUV pellicle for protecting the EUV mask has many obstacles due to high extinction coefficient of EUV wavelength. Recently researchers in the industry of semiconductor argue about the necessity of EUV pellicle and make effort to achieve it. In this paper, we investigated that the relationship between imaging performance and transmittance of EUV pellicle quantitatively. We made in-house EUV pellicle and analyzed its imaging performance of the dependence of pellicle transmittance using Coherent Scattering Microscopy(CSM). The imaging performance of EUV mask with pellicle is affected by its transmittance and we found that the performance of EUV mask improved with higher transmittance pellicle.

• Journal of the Korean Physical Society
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• v.73 no.12
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• pp.1879-1883
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• 2018

We analyzed the deep-trap states of GaN/InGaN ultraviolet light-emitting diodes (UV LEDs) before and after electrical stress. After electrical stress, the light output power dropped by 5.5%, and the forward leakage current was increased. The optical degradation mechanism could be explained based on the space-charge-limited conduction (SCLC) theory. Specifically, for the reference UV LED (before stress), two sets of deep-level states which were located 0.26 and 0.52 eV below the conduction band edge were present, one with a density of $2.41{\times}10^{16}$ and the other with a density of $3.91{\times}10^{16}cm^{-3}$. However, after maximum electrical stress, three sets of deep-level states, with respective densities of $1.82{\times}10^{16}$, $2.32{\times}10^{16}cm^{-3}$, $5.31{\times}10^{16}cm^{-3}$ were found to locate at 0.21, 0.24, and 0.50 eV below the conduction band. This finding shows that the SCLC theory is useful for understanding the degradation mechanism associated with defect generation in UV LEDs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.166-171
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• 2016

Nickel silicide is main issue in Polycrystalline silicon Thin Film Transistor (TFT) which is made by Metal Induced Lateral Crystallization (MILC) method. This Nickel silicide acts as a defect center, and this defect is one of the biggest reason of the high leakage current. In this research, we fabricated polycrystalline TFTs with novel method called Edge Cut (EC). With this new fabrication method, we assumed that nickel silicide at the edge of the channel region is reduced. Electrical properties are measured and trap state density also calculated using Levinson & Proano method.