• 한국정보디스플레이학회:학술대회논문집
• /
• 2006.08a
• /
• pp.1539-1543
• /
• 2006

We have developed self-aligned imprint lithography (SAIL) technology, an innovative method for roll-to-roll (R2R) fabrication of electronic devices on flexible plastic substrates. In this paper, we present the first R2R-produced ${\alpha}$-Si TFTs built on a polyimide substrate using the SAIL process, and prove the feasibility of this technology to enable R2R fabrication of flexible display active matrix (AM) backplanes with high precision and throughput.

• Proceedings of the KIEE Conference
• /
• 1989.07a
• /
• pp.655-658
• /
• 1989

The characteristics of proton-diffused $LiNbO_3$ optical waveguides with self-aligned $SiO_2$-cladding are reported. When the proton diffusion occurs, the $SiO_2$-cladding limits the lateral diffusion of protons by out-diffusion of protons in unclad region. Proton indiffusion in depth direction is promoted by inhibition of out-diffusion in clad region. Consequently, the mode profile in depth direction can be nealy symmetric. The extent of the proton exchange was observed by measuring the infrared absorption peak at about $3500cm^{-1}$. It is confirmed that proton diffusion with $SiO_2$-cladding has structural excellency.

• Proceedings of the KIEE Conference
• /
• 1989.11a
• /
• pp.502-504
• /
• 1989

An electro-optic cutoff modulator with self-aligned electrode that utilizes a single-mode proton-diffused well-guided channel waveguide in a X-cut Y-propagating $LiNbO_3$ substrate is reported. The self-aligned electrode is formed during proton diffusion process of itself. Nearly linear voltage-intensity relationship has been observed. Over 90 % modulation has been achieved with applied voltage of 25 V.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.77-80
• /
• 2002

In this paper, InP-based HBTs have been optimally designed by numerical simulation and fabricated by the self-aligned process. The structure of HBT was designed in terms of the current gain*f$_{max}$ for the base and f$_{T}$*f$_{max}$ for the collector. The designed structure produced the current gain of about 50 and the cutoff frequency and the maximum oscillation frequency of 87GHz and 2940Hz respectively. In addition, we present a study of the vertical and lateral etching of InP with the mask sides parallel to the principal crystallographic axes, [0101 and (001). This etching characteristics arc used to fabricate self-aligned HBT structures with reduced parasitic effects.s.s.s.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.1
• /
• pp.146-151
• /
• 1995

We have studied the fabrication self aligned atmospheric pressure(AP) CVD a-Si thin film transistor with source-drain ohmic contact by using ion shower doping method. The conductivity is 6*10$^{-2}$S/cm when the acceleration voltage, doping time and doping temperature are 6kV, 90s and 350.deg. C, respectively. We obtained the field effect mobility of 1.3cm$^{2}$/Vs and the threshold voltage of 7V.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.29A no.2
• /
• pp.77-79
• /
• 1992

We propose a self-aligned and double recessed technique for GaAs power MESFETs application. The gate length and the wide recess width are defined by a selective removal of the SiN layer using reactive ion etching(RIE) while the depth of the channel is defined by chemical etching of GaAs layers. The threshold voltages and the saturation drain voltage could be sucessfully controlled using this technique. The lateral-etched distance increases with the dry etching time and the source-drain breakdown voltage of MESFET increases up to about 30V at a pinch-off condition. The electrical characteristics of a MESFET with a gate length of 2 x10S0-6Tm and a source-gate spacing of 33 x10S0-6Tm show maximum transconductance of 120 mS/mm and saturation drain current density of 170-190mA/mm at a gate voltage of 0.8V.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2002.08a
• /
• pp.305-308
• /
• 2002

Field emission from single-walled carbon nanotubes (SWNTs) aligned on a patterned gold surface is reported. The SWNTs emitters were prepared at room temperature by a self-assembly monolayer technique. SWNTs were cut into sub-micron length by sonication in an acidic solution. Cut SWNTs were attached on the gold surface by the reaction between the thiol groups and the gold surface. The field emission measurement showed that the turn-on field was 4.8 $V/{\mu}m$ at the emission current density of 10 ${\mu}A/cm^2$. The current density was 0.5 $mA/cm^2$ at 6.6 $V/{\mu}m$. This approach provides a novel route for fabricating CNT-based field emission displays.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2005.07a
• /
• pp.303-306
• /
• 2005

We report the self-aligned low temperature poly silicon (LTPS) TFT process using simple doping process. In conventional LTPS-TFT, the Lightly Doped Drain (LDD) doping and source/drain doping are processed separately by aligning the gate with the source and drain during the gate lithography step. This ne w process not only fabricates fully self-aligned low temperature poly silicon TFTs with symmetric LDD structure but also simplifies the process flow with combined source/drain doping and LDD doping in one step. LDD doping process can be achieved using only source/drain doping process according to the new structure. In this paper, the TFT characteristics of NMOS and PMOS using the new doping process will be discussed.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 1997.10a
• /
• pp.128-128
• /
• 1997

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.436-437
• /
• 2012

Double patterning technology (DPT) has been suggested as a promising candidates of the next generation lithography technology in FLASH and DRAM manufacturing in sub-40nm technology node. DPT enables to overcome the physical limitation of optical lithography, and it is expected to be continued as long as e-beam lithography takes place in manufacturing. Several different processes for DPT are currently available in practice, and they are litho-litho-etch (LLE), litho-etch-litho-etch (LELE), litho-freeze-litho-etch (LFLE), and self-aligned double patterning (SADP) [1]. The self-aligned approach is regarded as more suitable for mass production, but it requires precise control of sidewall space etch profile for the exact definition of hard mask layer. In this paper, we propose etch end point detection (EPD) in spacer etching to precisely control sidewall profile in SADP. Conventional etch EPD notify the end point after or on-set of a layer being etched is removed, but the EPD in spacer etch should land-off exactly after surface removal while the spacer is still remained. Precise control of real-time in-situ EPD may help to control the size of spacer to realize desired pattern geometry. To demonstrate the capability of spacer-etch EPD, we fabricated metal line structure on silicon dioxide layer and spacer deposition layer with silicon nitride. While blanket etch of the spacer layer takes place in inductively coupled plasma-reactive ion etching (ICP-RIE), in-situ monitoring of plasma chemistry is performed using optical emission spectroscopy (OES), and the acquired data is stored in a local computer. Through offline analysis of the acquired OES data with respect to etch gas and by-product chemistry, a representative EPD time traces signal is derived. We found that the SE-EPD is useful for precise control of spacer etching in DPT, and we are continuously developing real-time SE-EPD methodology employing cumulative sum (CUSUM) control chart [2].