• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.5
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• pp.769-776
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• 2023

In this paper, we designed an MLSA(Match-line Sense Amplifier) for low-power CAM(Content Addressable Memory). By using the MLSA and precharge controller, we reduced power consumption during CAM operation by employing a selective match-line charging technique to mitigate power consumption caused by mismatch. Additionally, we further reduced power consumption due to leakage current by terminating precharge early when a mismatch occurs during the search operation. The designed circuit exhibited superior performance compared to the existing circuits, with a reduction of 6.92% and 23.30% in power consumption and propagation delay time, respectively. Moreover, it demonstrated a significant decrease of 29.92% and 52.31% in product-delay-product (PDP) and energy-delay-product (EDP). The proposed circuit was validated using SPECTRE simulation with TSMC 65nm CMOS process.

• Resources Recycling
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• v.29 no.6
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• pp.114-124
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• 2020

In the cement industry, NOx emission is recognized as an important problem, and NOx reduction technologies can be divided into process change, staged combustion, low NOx burner, selective non-catalytic reduction and selective catalytic reduction method. The operation of the selective non-catalytic reduction method, which is the most used in the cement industry, is expected to make it difficult to meet the emission standards to be strengthened in the future, and it is necessary to improve equipment such as SCR and secure technologies. Recently, we are developing technologies for simultaneous application of SNCR and SCR, dust and denitrification filter technology, and removal technology using NO oxidation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.45-50
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• 2007

This paper proposes a low power selective data write (SDW) scheme for a phase-change random access memory (PRAM). The PRAM consumes large write power because large write currents are required during long time. At first, the SDW scheme reads a stored data during write operation. And then, it writes an input data only when the input and stored data are different. Therefore, it can reduce the write power consumption to a half. The 1K-bit PRAM test chip with $128{\times}8bits$ is implemented with a $0.8{\mu}m$ CMOS technology with a $0.8{\mu}m$ GST cell.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.4
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• pp.902-908
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• 2013

This paper suggests to compress data selectively for improvement of data compression efficiency, not to perform unconditional compression on data. Whether to compress or not is determined by selective data distinction. By doing so, we can avoid unnecessary compression in the case of low compression efficiency. Cutting down the unnecessary compression, we can improve the performance of the pre-compression algorithm. Especially, the data algorithm which was already compressed could not be compressed efficiently in many cases, even if apply compression algorithm again. Even in these cases, we don't have to compress data unnecessarily. We implemented the proposed function actually and performed experiments with implementation. The experimental results showed normal operation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.58-64
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• 2013

In this paper, two new flip-flop circuits with PCRAM latches that are FF-1 and FF-2, respectively, are proposed not to waste leakage during sleep time. Unlike the FF-1 circuit that has a normal PCRAM latch, the FF-2 circuit has a selective write latch that can reduce the switching activity in writing operation to save switching power at sleep-in moment. Moreover, a sequential sleep-in control is proposed to reduce the rush current peak that is observed at the sleep-in moment. From the simulation of storing '000000' to the PCRAM latch, we could verify that the proposed FF-1 and FF-2 consume smaller power than the conventional 45-nm FF if the sleep time is longer than $465{\mu}s$ and $95{\mu}s$, respectively, at $125^{\circ}C$. For the rush current peak, the sequential sleep-in control could reduce the current peak as much as 77%.

• Corrosion Science and Technology
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• v.19 no.4
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• pp.224-230
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• 2020

Stainless steel has excellent corrosion resistance. The drawback is that pitting occurs easily due to the concentration of chloride. In addition, corrosion of socket weld, which is structurally and chemically weaker than the other components of the pipe, occurs rapidly. Since these two phenomena overlap, pinhole leakage occurs frequently in the seawater pipe socket welds made of stainless steel at the power plants. To analyze this specific corrosion, a metallurgical analysis of the stainless steel socket welds, where the actual corrosion occurred during the power plant operation, was performed. The micro-structure and chemical composition of each socket weld were analyzed. In addition, selective corrosion of the specific micro-structure in a mixed dendrite structure comprising γ-austenite (gamma-phase iron) and δ-ferrite (iron at high temperature) was investigated based on the characteristic micro-morphology and chemical composition of the corroded area. Finally, the different corrosion stages and characteristics of socket weld corrosion are summarized.

• Journal of Fisheries and Marine Sciences Education
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• v.24 no.2
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• pp.137-145
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• 2012

In order to survey the conditions of bycatch and discards for a gape net, a series of filed surveys was carried out total 10 surveys on two gape nets operated in the coastal area of Jindo during July to November 2008. The all catches in each survey were measured the body length, weight after sorted species. The analysis of catch data was conducted to separate 'first operation' and 'general operation'. In this study, the first operation defined as hauling the fishing gears that soaked over 10 hours because of setting on the previous day. The general operation means the haul of fishing gears conducted at intervals of one of or two hours after first operation. The bycatch in this study is defined as the other species except for anchovy, and bycatch rate refers to the proportion of bycatch to total catch. From the survey results, the average bycatch rates on first operations were 50% and 51% for Masa-ri and Supum-ri areas in Jindo, respectively. Also, the average bycatch rates on general operation were 2% and 3% for Masa-ri and Supum-ri areas in Jindo, respectively. The proportion of anchovy to total catch caught represented 75.5%. It needs the research on the selective fishing technology to reduce the bycatch on the gape net fishery.

• Journal of Power Electronics
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• v.7 no.2
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• pp.118-123
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• 2007

This paper presents a new ZCS-PWM high frequency inverter. Zero current switching operation is achieved in the whole load range by using a simple auxiliary reverse blocking switch in parallel with series resonant capacitor. Dual duty cycle control scheme is used to provide a wide range of high frequency AC output power regulation that is important in many high frequency inverter applications. It found that a complete soft switching operation can be achieved even for low power setting ranges by introducing high-frequency dual duty cycle control scheme. The proposed high frequency inverter is more suitable for consumer induction heating(IH) applications. The operation and control principle of the proposed high frequency inverter are described and verified through simulated results.

• Journal of the Institute of Convergence Signal Processing
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• v.16 no.3
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• pp.83-89
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• 2015

Connected component labeling (CCL) is a mandatory step in image segmentation where objects are extracted and uniquely labeled. CCL is a computationally expensive operation and thus is often done in parallel processing framework to reduce execution time. Various parallel CCL methods have been proposed in the literature. Among them are NSZ label equivalence (NSZ-LE) method, modified 8 directional label selection (M8DLS) method, HYBRID1 method, and HYBRID2 method. Soh et al. showed that HYBRID2 outperforms the others and is the best so far. In this paper we propose a new hybrid parallel CCL algorithm termed as HYBRID3 that combines selective four directional label search (S4DLS) with label backtracking (LB). We show that the average percentage speedup of the proposed over M8DLS is around 60% more than that of HYBRID2 over M8DLS for various kinds of images.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.05a
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• pp.836-839
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• 2002

This paper describes the selective Boolean operations on non-manifold geometric models whose union and subtraction operations are communicative. These operations guarantee the same resulting shape in spite of change of the order of Boolean operations, and the integrity of the model for omission of some features. In addition, a B-rep model for a modified modeling history is obtained in a short time, as no boundary evaluation is necessary. These features enable easy implementation of multi-resolution representation of B-rep models.