Browse > Article

A Low Power Phase-Change Random Access Memory Using A Selective Data Write Scheme  

Yang, Byung-Do (School of Electrical and Computer Engineering, Chungbuk National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.44, no.1, 2007 , pp. 45-50 More about this Journal
Abstract
This paper proposes a low power selective data write (SDW) scheme for a phase-change random access memory (PRAM). The PRAM consumes large write power because large write currents are required during long time. At first, the SDW scheme reads a stored data during write operation. And then, it writes an input data only when the input and stored data are different. Therefore, it can reduce the write power consumption to a half. The 1K-bit PRAM test chip with $128{\times}8bits$ is implemented with a $0.8{\mu}m$ CMOS technology with a $0.8{\mu}m$ GST cell.
Keywords
VLSI; memory; PRAM; low power; write;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Woo Yeong Cho, et al., 'A $0.18-{\mu}m$ 3.0-V 64-Mb Nonvolatile Phase-Transition Rrandom Access Memory (PRAM),' IEEE J. Solid-State Circuits, Vol. 40, No. 1, pp. 293-300, Jan. 2005   DOI
2 Hyung-rok Oh, et al., 'Enhanced Write Performance of a 64-Mb Phase-Change Random Access Memory,' IEEE J. Solid-State Circuits, Vol. 41, No. 1, pp. 122-126, Jan. 2006   DOI   ScienceOn
3 Y. N. Hwang, et al, 'Full integration and reliability evaluation of phase-change RAM based on $0.24{\mu}m$-CMOS technologies,' Symp. VLSI Technology Dig., pp. 173-174, June 2003