• 제목/요약/키워드: Selective harmonic elimination

검색결과 32건 처리시간 0.022초

Selective Harmonic Elimination in Multi-level Inverters with Series-Connected Transformers with Equal Power Ratings

  • Moussa, Mona Fouad;Dessouky, Yasser Gaber
    • Journal of Power Electronics
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    • 제16권2호
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    • pp.464-472
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    • 2016
  • This study applies the selective harmonic elimination (SHE) technique to design and operate a regulated AC/DC/AC power supply suitable for maritime military applications and underground trains. The input is a single 50/60 Hz AC voltage, and the output is a 400 Hz regulated voltage. The switching angles for a multi-level inverter and transformer turns ratio are determined to operate with special connected transformers with equal power ratings and produce an almost sinusoidal current. As a result of its capability of directly controlling harmonics, the SHE technique is applicable to apparatus with congenital immunity to specific harmonics, such as series-connected transformers, which are specially designed to equally share the total load power. In the present work, a single-phase 50/60 Hz input source is rectified via a semi-controlled bridge rectifier to control DC voltage levels and thereby regulate the output load voltage at a constant level. The DC-rectified voltage then supplies six single-phase quazi-square H-bridge inverters, each of which supplies the primary of a single-phase transformer. The secondaries of the six transformers are connected in series. Through off-line calculation, the switching angles of the six inverters and the turns ratios of the six transformers are designed to ensure equal power distribution for the transformers. The SHE technique is also employed to eliminate the higher-order harmonics of the output voltage. A digital implementation is carried out to determine the switching angles. Theoretical results are demonstrated, and a scaled-down experimental 600 VA prototype is built to verify the validity of the proposed system.

A New Scheme for Maintaining Balanced DC Voltages in Static Var Compensator(SVC) Using Cascade Multilevel Inverter

  • Min, Wan-Ki;Min, Joon-Ki;Choi, Jae-Ho
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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    • pp.561-565
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    • 2001
  • This paper proposes a new switching scheme of a static var compensator(SVC) with cascade multilevel inverter which employs H-bridge inverter(HBI). To improve the un­balanced problem of the DC capacitor voltages, the rotated switching scheme of fundamental frequency is newly used. The optimized fundamental switching pattern with low switching frequency is adapted to be suitable for high application. The selective harmonic elimination method(SHEM) allows to keep the total harmonic distortion(THD) low in the output voltage of multilevel inverter. The SVC system is modeled using the d-q transform which calculates the instantaneous reactive power. This model is used to design a controller and analyze the SVC system. Simulated and experimental results are also presented and discussed to validate the proposed schemes.

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직렬형 멀티레벨 인버터를 사용한 무효전력보상장치의 직류전압평형을 위한 새로운 제어기법 (A New Control Scheme for Maintaining Balanced DC Voltages in Static Var Compensator(SVC) Using Cascade Multilevel Inverter)

  • 민완기;민준기;최재호
    • 전기학회논문지P
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    • 제54권4호
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    • pp.179-184
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    • 2005
  • This paper examines the application of high voltage static var compensator(SVC) with cascade multilevel inverter which employs H-bridge inverter(HBI). A new switching scheme is developed for the SVC system. To improve the unbalanced problem of the DC capacitor voltages, the rotated switching scheme of fundamental frequency is newly used. The optimized fundamental switching pattern with low switching frequency is adapted to be suitable for high application. The selective harmonic elimination method(SHEM) allows to keep the total harmonic distortion(THD) low in the output voltage of multilevel inverter. The SVC system is modeled using the d-q transform which calculates the instantaneous reactive power. This model is used to design a controller and analyze the SVC system. Simulated and experimental results are also presented and discussed to validate the proposed schemes.

대전력용 직렬형 멀티레벨 인버터 이용한 STATCOM의 새로운 제어기법 (Novel Control of STATCOM Using Cascade Multilevel Inverter for High Power Application)

  • 민완기;최재호
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2000년도 학술대회 논문집 전문대학교육위원
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    • pp.136-141
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    • 2000
  • This paper proposes the novel control of a static synchronous compensator (STATCOM). This STATCOM system consists of cascade multilevel inverter which employs H-bridge inverter(HBI) The STATCOM system is modeled in the d-q transform matrix. This model is used to design a controller. The selective harmonic elimination method(SHEM) allows to keep the total harmonic distortion (THD) low in the output voltage. The switching method produces the staircase type waveform in cascade multilevel inverter. To balance the DC voltages in HBIs capacitor, the rotated switching scheme is newly proposed in this paper. The proposed control scheme is verified in the simulated results.

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직렬형 멀티레벨 인버터를 사용한 무효전력보상장치의 새로운 직류전압 평형기법 (A New Scheme for Maintaining Balanced DC Voltages in Static Var Compensator(SVC))

  • 민완기;민준기;최재호
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2003년도 학술대회 논문집 전문대학교육위원
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    • pp.144-148
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    • 2003
  • This paper examines the application of high voltage static var compensator(SVC) with cascade multilevel inverter which employs H-bridge inverter(HBI). To improve the unbalanced problem of the DC capacitor voltages, the rotated switching scheme of fundamental frequency is newly used. The optimized fundamental switching pattern with low switching frequency is adapted to be suitable for high application. The selective harmonic elimination method(SHEM) allows to keep the total harmonic distortion(THD) low in the output voltage of multilevel inverter. The SVC system is modeled using the d-q transform which calculates the instantaneous reactive power. This model is used to design a controller and analyze the SVC system. Simulated and experimental results are also presented and discussed to validate the proposed schemes.

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Walsh-Fourier 변환을 사용한 PWM 인버어터의 고조파 제거 방법 (A Harmonic Elimination Method of PWM Inverter Using Walsh-Fourier Transform)

  • 안두수;원충연;이해기;김태훈;김학성
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1989년도 추계학술대회 논문집 학회본부
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    • pp.296-300
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    • 1989
  • The paper proposes a method to eliminate harmonics of PWM inverter fed induction motor system using Walsh series. In other words, this paper presents technique of the selective harmonics elimination(SHE) by W-FT series in three phase PWM inverter output waveform. A microprocessor(8086 CPU) - controlled three phase induction motor system in order to verify this algorithm is present. It is designed for a three output voltage in the 1$\sim$60 Hz inverter with the 5th and 7th harmonics, 5th, 7th, 11th, and 13th, harmonics eliminated, and with the fundamental wave amplitude proportional to the output frequency. In the PWM inverter, dead time circuit is inserted in the switching si gnats to prevent the de link shortage. This paper is deals with quantative prediction of dead-time effect and its compensation in PWM inverters. The performance of the compensation circuits is confirmed by the experiment.

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축소모형을 이용한 MMC의 Redundancy Module 동작분석 (Redundancy Module Operation Analysis of MMC using Scaled Hardware Model)

  • 유승환;신은석;최종윤;한병문
    • 전기학회논문지
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    • 제63권8호
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    • pp.1046-1054
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    • 2014
  • In this paper, a hardware prototype for the 10kVA 11-level MMC was built and various experimental works were conducted to verify the operation algorithms of MMC. The hardware prototype was designed using computer simulation with PSCAD/EMTDC software. After manufactured in the lab, the hardware prototype was tested to verify the modulation algorithms to form the output voltage, the balancing algorithm to equalize the sub-module capacitor voltage, and the redundancy operation algorithm to improve the system reliability. The developed hardware prototype can be utilized for analyzing the basic operation and performance improvement of MMC according to the modulation and redundancy operation scheme. It also can be utilize to analyze the basic operational characteristics of HVDC system based on MMC.

Hybrid PWM Modulation Technology Applied to Three-Level Topology-Based PMSMs

  • Chen, Yuanxi;Guo, Xinhua;Xue, Jiangyu;Chen, Yifeng
    • Journal of Power Electronics
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    • 제19권1호
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    • pp.146-157
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    • 2019
  • The inverter is an essential part of permanent magnet synchronous motor (PMSM) drive systems. The performance of an inverter is greatly influenced by its modulation strategy. Using a proper management of modulation strategies can guarantee high performance from a PMSM under various speed conditions. Switching between modulations is a pivotal technique that determines the performance of a PMSM. Most works on hybrid methods focus on two-level induction motors drive systems. In this paper, in order to improve the performance of PMSMs under various speed conditions, a hybrid method of a pulse width modulation (PWM) control scheme based on a neutral-point-clamped (NPC) three level topology was proposed. This hybrid PWM modulation comprised space vector PWM (SVPWM) and selective harmonic elimination PWM (SHEPWM). Under low speed conditions, the SVPWM is employed to cause the PMSM to start smoothly, and to obtain a rapid response from the control system. Under high speed conditions, the SHEPWM is employed to reduce the switching frequency and to eliminate particular current harmonics. Moreover, the harmonic characteristics of different modulations are analyzed to obtain a smooth transition between the SHEPWM and the SVPWM. Experimental and simulation results indicated the effectiveness of the proposed control method.

A New Single-Phase Asymmetrical Cascaded Multilevel DC-Link Inverter

  • Ahmed, Mahrous;Hendawi, Essam
    • Journal of Power Electronics
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    • 제16권4호
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    • pp.1504-1512
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    • 2016
  • This paper presents a new single-phase asymmetrical cascaded multilevel DC-link inverter. The proposed inverter comprises two stages. The main stage of the inverter consists of multiple similar cells, each of which is a half-bridge inverter consisting of two switches and a single DC source. All cells are connected in a cascaded manner with a fixed neutral point. The DC source values are not made equal to increase the performance of the inverter. The second circuit is a folded cascaded H-bridge circuit operating at a line frequency. One of the main advantages of this proposed topology is that it is a modular type and can thus be extended to high stages without changing the configuration of the main stage circuit. Two control schemes, namely, low switching with selective harmonic elimination and sinusoidal pulse width modulation, are employed to validate the proposed topology. The detailed approach of each control scheme and switching pulses are discussed in detail. A 150W prototype of the proposed system is implemented in the laboratory to verify the validity of the proposed topology.

단상 PV 인버터용 온-라인 데드타임 보상기 연구 (A New On-Line Dead-Time Compensator for Single-Phase PV Inverter)

  • 부우충기엔;차한주
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2010년도 하계학술대회 논문집
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    • pp.216-217
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    • 2010
  • This paper presents a new software-based on-line dead-time compensation technique for single-phase grid-connected photovoltaic (PV) inverter system. To improve the mitigation of dead-time effect around the zero-crossing point of phase current, a selective harmonic elimination of instantaneous feedback current is used as an additional part of conventional current control scheme. Simulation and experimental results are shown to verify the effectiveness of proposed compensation method in the grid-connected power distributed generation systems.

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