• ETRI Journal
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• v.25 no.6
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• pp.503-509
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• 2003

Selective epitaxial growth (SEG) of silicon has attracted considerable attention for its good electrical properties and advantages in building microstructures in high-density devices. However, SEG problems, such as an unclear process window, selectivity loss, and nonuniformity have often made application difficult. In our study, we derived processing diagrams for SEG from thermodynamics on gas-phase reactions so that we could predict the SEG process zone for low pressure chemical vapor deposition. In addition, with the help of both the concept of the effective supersaturation ratio and three kinds of E-beam patterns, we evaluated and controlled selectivity loss and non-uniformity in SEG, which is affected by the loading effect. To optimize the SEG process, we propose two practical methods: One deals with cleaning the wafer, and the other involves inserting dummy active patterns into the wide insulator to prevent the silicon from nucleating.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.9-10
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• 2005

Process diagrams of selective epitaxial growth of silicon(SEG) could be developed from CVD thermodynamics. They could not only be helpful with understanding of the mechanism, but also offer good processing guidelines in manufacturing high density devices. Through the process optimization skill, applications of SEG to high-density device structures could be possible without problems such as loading effect and facet generation, with producing outstanding electronic properties.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.7
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• pp.573-578
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• 2003

Low temperature selective epitaxial growth of Si and SiGe has been obtained using an industrial single wafer chemical vapor deposition module operating at reduced pressure. Epitaxial Si and heteroepitaxial SiGe deposition with Ge content about 20 % has been studied as extrinsic base for self-aligned heterojunction bipolar transistors(HBTs), which helps to reduce the parasitic resistance to obtain higher maximum oscillation frequencies(f$\_$max/). The dependence of Si and SiGe deposition rates on exposed windows and their evolution with the addition of HCl to the gas mixture are investigated. SiH$_2$Cl$_2$ was used as the source of Si SEG(Selective Epitaxial Growth) and GeH$_4$ was added to grow SiGe SEG. The addition of HCl into the gas mixture allows increasing an incubation time even low growth temperature of 675∼725$^{\circ}C$. In addition, the selectivity is enhanced for the SiGe alloy and it was proposed that the incubation time for the polycrystalline deposit on the oxide is increased probably due to GeO formation. On the other hand, when only SiGe SEG(Selective Epitaxial Growth) layer is used for extrinsic base, it shows a higher sheet resistance with Ti-silicide because of Ge segregation to the interface, but in case of Si or Si/SiGe SEG layer, the sheet resistance is decreased up to 70 %.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1025-1027
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• 1995

SEG(Selective Epitaxial Growth) and ELO(Epitaxial Lateral Growth) of Silicon offer new opportunities in the fabrication of MEMS(Micro Electro-Mechanical Systems) structures. SEG of silicon enables the stacking of junctions in addition to those resulting from the standard bipolar process and this properly was utilized for the fabrication of an improved-performance color sensor. When the crystalline growth takes place through the seed windows and proceeds over the dielectric, after reaching the surface, it form an ELO silicon layer and this ELO-Si can be modified into various structures for MEMS application such as cantilevers, beams, diaphragms.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1357-1359
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• 2001

0.2${\mu}m$ 이하의 최소 선폭을 가지는 소자를 구현할 때 drain induced barrier lowering (DIBL)이나 hot electron effect와 같은 short channel effect (SCE)가 나타나며 이로 인하여 소자의 신뢰성이 악화되기도 한다. 이를 개선하기 위한 방법 중 하나가 silicon selective epitaxial growth (SEG)를 이용한 elevated source/drain (ESD) 구조이다. 본 연 구에서는 silicon selective epitaxial growth를 이용하여 elevated source/drain 구조를 갖는 MOSFET 소자와 일반적인 MOSFET 구조를 갖는 소자와의 차이를 elevated source/drain의 높이 변화에 따른 전류 전압 특성을 이용하여 비교, 분석하였으며 그 결과 elevated source/drain 구조가 short channel effect를 감소시킴을 확인할 수 있었다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.24.2-24.2
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• 2009

Nanostuctures such as nanodot and nanowire have been extensively studied as building blocks for nanoscale devices. However, the direct growth of the nanostuctures at the desired position is one of the most important requirements for realization of the practical devices with high integrity. Self-assembled nanotemplate is one of viable methods to produce highly-ordered nanostructures because it exhibits the highly ordered nanometer-sized pattern without resorting to lithography techniques. And selective epitaxial growth (SEG) can be a proper method for nanostructure fabrication because selective growth on the patterned openings obtained from nanotemplate can be a proper direction to achieve high level of control and reproducibility of nanostructucture fabrication. Especially, SiGe has led to the development of semiconductor devices in which the band structure is varied by the composition and strain distribution, and nanostructures of SiGe has represented new class of devices such nanowire metal-oxide-semiconductor field-effect transistors and photovoltaics. So, in this study, various shaped SiGe nanostructures were selectively grown on Si substrate through ultrahigh vacuum chemical vapor deposition (UHV-CVD) of SiGe on the hexagonally arranged Si openings obtained using nanotemplates. We adopted two types of nanotemplates in this study; anodic aluminum oxide (AAO) and diblock copolymer of PS-b-PMMA. Well ordered and various shaped nanostructure of SiGe, nanodots and nanowire, were fabricated on Si openings by combining SEG of SiGe to self-assembled nanotemplates. Nanostructure fabrication method adopted in this study will open up the easy way to produce the integrated nanoelectronic device arrays using the well ordered nano-building blocks obtained from the combination of SEG and self-assembled nanotemplates.

• Journal of the Korean Vacuum Society
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• v.11 no.1
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• pp.16-21
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• 2002

Selective epitaxial growth(SEG) of silicon were performed at low temperature under an ultraclean environment below $1000^{\circ}C$ using ultraclean $Si_2H_6$ and $H_2$ gases ambient in low pressure chemical vapor deposition(LPCVD). As a result of ultraclean processing, epitaxial Si layers with good quality were obtained for uniform and SEG wafer at temperatures range 600~$710^{\circ}C$ and an incubation period of Si deposition only on $SiO_2$ was found. Low-temperature Si selectivity deposition condition and epitaxy on Si were achieved without addition of HCl. The epitaxial layer was found to be thicker than the poly layer deposited over the oxide. Incubation period prolonged for 20~30 sec can be obtained by $O_2$addition. The surface morphologies & cross sections of the deposited films were observed with SEM, The structure of the Si films was evaluated XRD.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.3
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• pp.134-140
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• 2002

Deep submicron NMOSFETs with elevated source/drain can be fabricated using self-aligned selective epitaxial growth(SEG) of silicon for enhanced device characteristics with shallow junction compared to conventional MOSFETs. Shallow junctions, especially with the heartily-doped S/D residing in the elevated layer, give hotter immunity to Yt roll off, drain-induced-barrier-lowering (DIBL), subthreshold swing (SS), punch-through, and hot carrier effects. In this paper, the characteristics of both deep submicron elevated source/drain NMOSFETs and conventional NMOSFETs were investigated by using TSUPREM-4 and MEDICI simulators, and then the results were compared. It was observed from the simulation results that deep submicron elevated S/D NMOSFETs having shallower junction depth resulted in reduced short channel effects, such as DIBL, SS, and hot carrier effects than conventional NMOSFETs. The saturation current, Idsat, of the elevated S/D NMOSFETs was higher than conventional NMOSFETs with identical device dimensions due to smaller sheet resistance in source/drain regions. However, the gate-to-drain capacitance increased in the elevated S/D MOSFETs compared with the conventional NMOSFETs because of increasing overlap area. Therefore, it is concluded that elevated S/D MOSFETs may result in better device characteristics including current drivability than conventional NMOSFETs, but there exists trade-off between device characteristics and fate-to-drain capacitance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.114-118
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• 2006

In this paper, the effect of base and collector structures on DC, small signal characteristics of SiGe HBTs fabricated by RPCVD was investigated. The structure of SiGe HBTs was designed into four types as follows: SiGe HBT structures which are standard, apply extrinsic-base SEG selective epitaxial growth (SEG), apply selective collector implantation (SCI), and apply both extrinsic-base SEG and SCI. We verified the devices could be applied to the fabrication of RFIC chip through a fully integrated 2.4 GHz down-conversion mixer.

• ETRI Journal
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• v.25 no.4
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• pp.247-252
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• 2003

This paper presents results from experiments on laser-annealed SiGe-selective epitaxial growth (LA-SiGe-SEG). The SiGe-SEG technology is attractive for devices that require a low band gap and high mobility. However, it is difficult to make such devices because the SiGe and the highly doped region in the SiGe layer limit the thermal budget. This results in leakage and transient enhanced diffusion. To solve these problems, we grew in situ doped SiGe SEG film and annealed it on an XMR5121 high power XeCl excimer laser system. We successfully demonstrated this LA-SiGe-SEG technique with highly doped Ge and an ultra shallow junction on p-type Si (100). Analyzing the doping profiles of phosphorus, Ge compositions, surface morphology, and electric characteristics, we confirmed that the LA-SiGe-SEG technology is suitable for fabricating high-speed, low-power devices.