• 한국재료학회:학술대회논문집
• /
• 한국재료학회 1999년도 추계학술발표강연 및 논문개요집
• /
• pp.138-138
• /
• 1999

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
• /
• pp.151-154
• /
• 2007

We demonstrate a novel selective patterning process of a semiconducting polymer for channel regions to fabricate an array of organic thin-film transistors (OTFTs). This process is applicable for various organic films over large area. A reflective liquid crystal display based on the OTFT array was produced using the selective patterning through a wettability control.

• Journal of Power Electronics
• /
• 제15권4호
• /
• pp.964-973
• /
• 2015

This paper presents a simple approach for the selective harmonic elimination (SHE) of multilevel inverter based on the transistor-clamped H-bridge (TCHB) family. The SHE modulation is derived from the sinusoidal voltage-angle equal criteria corresponding to the optimized switching angles. The switching angles are computed offline by solving transcendental non-linear equations characterizing the harmonic contents using the Newton-Raphson method to produce an optimum stepped output. Simulation and experimental tests are conducted for verification of the analytical solutions. An Altera DE2 field-programmable gate array (FPGA) board is used as the digital controller device in order to verify the proposed SHE modulation in real-time applications. An analysis of the voltage total harmonic distortion (THD) has been obtained for multiple output voltage cases. In terms of the THD, the results showed that the higher the number of output levels, the lower the THD due to an increase number of harmonic orders being eliminated.

• 한국전기전자재료학회논문지
• /
• 제19권11호
• /
• pp.1005-1009
• /
• 2006

High quality three-dimensional (3D) heterostructures were constructed by selective area (SA) molecular beam epitaxy (MBE) using a specially patterned GaAs (001) substrate to improve the efficiency of tarrier transport. MBE growth parameters such as substrate temperature, V/III ratio, growth ratio, group V sources (As2, As4) were varied to calibrate the selective area growth conditions and the 3D GaAs-AlGaAs heterostructures were fabricated into the ridge type and the V-groove type. Scanning micro-photoluminescence $({\mu}-PL)$ measurements and the following analysis revealed that the gradually (adiabatically) coupled 1D-2DEG (electron gas) field effect transistor (FET) system was successfully realized. These 3D-heterostructures are expected to be useful for the realization of high-performance mesoscopic electronic devices and circuits since it makes it possible to form direct ohmic contact onto the (quasi) 1D electron channel.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
• /
• pp.167-168
• /
• 2006

High quality 3D-heterostructures were constructed by selective area (SA) molecular beam epitaxy (MBE) using a specially patterned GaAs (001) substrate. MBE growth parameters such as substrate temperature, V/III ratio, growth ratio, group V sources ($As_2$, $As_4$) were varied to calibrate the selective area growth conditions. Scanning micro-photoluminescence ($\mu$-PL) measurements and following analysis revealed that the gradually (adiabatically) coupled 2DEG-1D-1DEG field effect transistor (FET) system was realized. This 3D-heterostructure is very promising for the realization of the meso-scopic electronic devices and circuits since it makes it possible to form direct ohmic contact to the (quasi) 1DEG.

• 마이크로전자및패키징학회지
• /
• 제24권3호
• /
• pp.7-11
• /
• 2017

본 논문은 3차원 낸드 플래쉬 기억 소자에 적용을 위해 소노스(SONOS) 형태로 기억 저장 절연막을 채용하고 채널로 폴리실리콘을 사용한 박막형 트랜지스터에 대해 연구하였다. 셀의 source/drain에는 불순물을 주입 하지 않았고, 셀 양 끝단에는 선택 트랜지스터를 배치하였다. 셀의 채널과 선택 트랜지스터의 source/drain 불순물 농도 변화에 대한 평가를 진행하여 공정 최적화를 하였다. 선택 트랜지스터의 농도 증가 시 채널 전류의 상승 및 삭제특성이 개선됨을 확인 하였는데 이는 GIDL에 의한 홀 생성이 증가하였기 때문이다. 최적화된 공정 변수에 대해 삭제와 쓰기 후 문턱전압의 프로그램 윈도우는 대략 2.5V를 얻었다. 터널 산화막 공정 온도에 대한 평가 결과 온도 증가 시 swing 및 신뢰성 항목인 bake 결과가 개선됨을 확인하였다.

• 전자통신동향분석
• /
• 제38권6호
• /
• pp.52-61
• /
• 2023

With semiconductor scaling approaching the physical limits, devices including CMOS (complementary metal-oxide-semiconductor) components have managed to overcome yet are currently struggling with several technical issues like short-channel effects. Evolving from the process node of 22 nm with FinFET (fin field effect transistor), state-of-the-art semiconductor technology has reached the 3 nm node with the GAA-FET (gate-all-around FET), which appropriately addresses the main issues of power, performance, and cost. Technical problems remain regarding the foundry of GAA-FET, and next-generation devices called post-GAA transistors have not yet been devised, except for the CFET (complementary FET). We introduce a CFET that spatially stacks p- and n-channel FETs on the same footprint and describe its structure and fabrication. Technical details like stacking of nanosheets, special spacers, hetero-epitaxy, and selective recess are more thoroughly reviewed than in similar articles on CFET fabrication.

• 한국생산제조학회지
• /
• 제24권1호
• /
• pp.135-139
• /
• 2015

We present a fine patterning method of conductive lines on polyimide (PI) and glass substrates using silver (Ag) nanoparticles based on laser scanning. Controlled laser irradiation can realize selective sintering of conductive ink without damaging the substrate. Thus, this technique easily creates fine patterns on heat-sensitive substrates such as flexible plastics. The selective laser sintering of Ag nanoparticles was managed by optimizing the conditions for the laser scan velocity (1.0-20 mm/s) and power (10-150 mW) in order to achieve a small gap size, high electrical conductivity, and fine roughness. The fabricated electrodes had a minimum channel length of $5{\mu}m$ and conductivity of $4.2{\times}10^5S/cm$ (bulk Ag has a conductivity of $6.3{\times}10^5S/cm$) on the PI substrate. This method was used to successfully fabricate an organic field effect transistor with a poly(3-hexylthiophene) channel.

• 한국정보통신학회논문지
• /
• 제24권2호
• /
• pp.321-324
• /
• 2020

In this work, we developed a selective etching process for GaN that is a key process in p-GaN/AlGaN/GaN enhancement-mode (E-mode) power switching field-effect transistor (FET) fabrication. In order to achieve a high current density of p-GaN/AlGaN/GaN E-mode FET, the p-GaN layer beside the gate region must be selectively etched whereas the underneath AlGaN layer should be maintained. A selective etching process was implemented by oxidizing the surface of the AlGaN layer and the GaN layer by adding O2 gas to Cl2/N2 gas which is generally used for GaN etching. A selective etching process was optimized using Cl2/N2/O2 gas mixture and a high selectivity of 53:1 (= GaN/AlGaN) was achieved.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2010년도 춘계학술대회 논문집
• /
• pp.40-40
• /
• 2010

CdSe nanocrystals (NCs) have been decorated on singlewalled carbon nanotubes (SWCNTs) by combining a method of chemically modified substrate along with gate-bias control. CdSe/ZnS core/shell quantum dots were negatively charged by adding mercaptoacetic acid (MAA). The silicon oxide substrate was decorated by octadecyltrichlorosilane (OTS) and converted to hydrophobic surface. The negatively charged CdSe NCs were adsorbed on the SWCNT surface by applying the negative gate bias. The selective adsorption of CdSe quantum dots on SWCNTs was confirmed by confocal laser scanning microscope. The measured photocurrent clearly demonstrates that CdSe NCs decorated SWCNT can be used for photodetector and solar cell that are operable over a wide range of wavelengths.