• 전기전자학회논문지
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• 제22권2호
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• pp.484-487
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• 2018

5 MeV proton-irradiation with total dose of $10^{15}/cm^2$ was performed on AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) with various gate metals including Ni, TaN, W, and TiN to investigate the degradation characteristics. The positive shift of pinch-off voltage and the reduction of on-current were observed from irradiated HEMTs regardless of a type of gate materials. Hall and transmission line measurements revealed the reduction of carrier mobility and sheet charge concentration due to displacement damage by proton irradiation. The shift of pinch-off voltage was dependent on Schottky barrier heights of gate metals. Gate leakage and capacitance-voltage characteristics did not show any significant degradation demonstrating the superior radiation hardness of Schottky gate contacts on GaN.

• 한국재료학회지
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• 제24권3호
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• pp.135-139
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• 2014

To obtain the transistor with ambipolar transfer characteristics, IGZO/SiOC thin film transistor was prepared on SiOC with various polarities as a gate insulator. The interface between a channel and insulator showed the Ohmic and Schottky contacts in the bias field of -5V ~ +5V. These contact characteristics depended on the polarities of SiOC gate insulators. The transfer characteristics of TFTs were observed the Ohmic contact on SiOC with polarity, but Schottky contact on SiOC with low polarity. The IGZO/SiOC thin film transistor with a Schottky contact in a short range bias electric field exhibited ambipolar transfer characteristics, but that with Ohmic contact in a short range electric field showed unipolar characteristics by the trapping phenomenon due to the trapped ionized defect formation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.152-159
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• 2010

We propose a semi-analytical current conduction model for depletion-mode n-type nanowire field-effect transistors (NWFETs) with top-gate structure. The NWFET model is based on an equivalent circuit consisting of two back-to-back Schottky diodes for the metal-semiconductor (MS) contacts and the intrinsic top-gate NWFET. The intrinsic top-gate NWFET model is derived from the current conduction mechanisms due to bulk charges through the center neutral region as well as of accumulation charges through the surface accumulation region, based on the electrostatic method, and thus it includes all current conduction mechanisms of the NWFET operating at various top-gate bias conditions. Our previously developed Schottky diode model is used for the MS contacts. The newly developed model is integrated into ADS, in which the intrinsic part of the NWFET is developed by utilizing the Symbolically Defined Device (SDD) for an equation-based nonlinear model. The results simulated from the newly developed NWFET model reproduce considerably well the reported experimental results.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.221-225
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• 2016

This paper reports a new method to enable the normally-off operation of AlGaN/GaN heterojunction field-effect transistors (HFETs). A capacitor was connected to the gate input node of a normally-on AlGaN/GaN HFET with a Schottky gate where the Schottky gate acted as a clamping diode. The combination of the capacitor and Schottky gate functioned as a clamp circuit to downshift the input signal to enable the normally-off operation. The normally-off operation with a virtual threshold voltage of 5.3 V was successfully demonstrated with excellent dynamic switching characteristics.

• EDISON SW 활용 경진대회 논문집
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• 제6회(2017년)
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• pp.398-403
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• 2017

본 연구에서는 gate-all-around(GAA) 수직 나노선 Field-Effect Transistor(FET)의 소스/드레인 반도체/실리사이드 접합에 존재하는 Schottky 장벽이 트랜지스터의 DC특성에 미치는 영향에 대하여 조사하였다. Non-Equilibrium Green's Function와 Poisson 방정식 기반의 시뮬레이터를 사용하여, Schottky 장벽의 위치와 높이, 그리고 채널 단면적의 크기에 따른 전류-전압 특성 곡선과 에너지 밴드 다이어그램을 통해 분석을 수행하였다. 그 결과, 드레인 단의 Schottky 장벽은 드레인 전압에 의해 장벽의 높이가 낮아져 전류에 주는 영향이 작지만, 소스 단의 Schottky 장벽은 드레인 전압과 게이트 전압으로 제어가 불가능하여 외부에서 소스 단으로 들어오는 캐리어의 이동을 방해하여 큰 DC성능 저하를 일으킨다. 채널 단면적 크기에 따른 DC특성 분석 결과로는 동작상태의 전류밀도는 채널의 폭이 5 nm 일 때까지는 유지되고, 2 nm가 되면 그 크기가 매우 작아지지만, 채널 단면적은 Schottky 장벽에 영향을 끼치지 못하였다. 본 논문의 분석 결과로 향후 7 nm technology node 에 적용될 GAA 수직 나노선 FET의 소자 구조 설계에 도움이 되고자 한다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.287.2-287.2
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• 2016

Silicon has considerably good characteristics on electron, hole mobility and its price. With 2-D sinlge-layer Graphene/n-Si heterojunction solar cell shows that in one sun condition exhibit power conversion efficiency(PCE) of 10.1%. This photovoltaic effect was achieved by applying gate voltage to the Schottky junction of the heterostructure solar cell. Energy band diagram shows that Schottky barrier between Si and graphene can be adjust by the external electric field. because of the fermi level of the graphene can be changed by external gate voltage, we can control the Schottkky barrier of the heterostructure solar cell. The ratio between generated power of solar cell and consumption electrical power is remarkable. Since we use the graphene as the top gate electrode, most of the sun light can penetrate into the active area.

• 한국산학기술학회논문지
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• 제11권2호
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• pp.485-490
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• 2010

본 논문에서는 버팅 콘택(butting contact) 구조를 갖는 DDI DRAM소자의 감지 증폭기의 입력 게이트 단의 모든 기생 성분을 포함한 등가 회로를 제안 하였다. 제안한 모델을 이용하여 기생 쇼트키 다이오드가 감지 증폭기 동작에 어떤 영향을 미치는지 분석하였다. 각각의 불량 가능성에 대해 감지 증폭기가 어떻게 동작하는지 분석하여 단측 불량 특성의 원인을 규명하였다. DDI DRAM에서 단측 불량 원인과 불량률의 온도 의존성은 감지 증폭기의 입력 게이트 단에 형성된 기생 쇼트키 다이오드 형성에 기인한 것으로 판단된다. 이러한 기생 쇼트키 다이오드는 게이트 입력에 기생 전압 강하를 야기하게 되고 결국 감지 증폭기의 노이즈 마진을 감소시켜 단측 불량률을 증가시킨다.

• 한국재료학회지
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• 제13권1호
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• pp.11-17
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• 2003

DC characteristics of recessed gate 4H-SiC MESFET were investigated using the device/circuit simulation tool, PISCES. Results of theoretical calculation were compared with the experimental data for the extraction of modeling parameters which were implemented for the prediction of DC and gate leakage characteristics at high temperatures. The current-voltage analysis using a fixed mobility model revealed that the short channel effect is influenced by the defects in SiC. The incomplete ionization models are found out significant physical models for an accurate prediction of SiC device performance. Gate leakage is shown to increase with the device operation temperatures and to decrease with the Schottky barrier height of gate metal.

• Transactions on Electrical and Electronic Materials
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• 제16권4호
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• pp.187-189
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• 2015

A charge-trap flash (CTF) thin film transistor (TFT) memory is proposed at a low-temperature process (≤ 450℃). The memory cell consists of a sputtered oxide-nitride-oxide (ONO) gate dielectric and Schottky barrier (SB) source/drain (S/D) junctions using nickel silicide. These components enable the ultra-low-temperature process to be successfully achieved with the ONO gate stacks that have a substrate temperature of room temperature and S/D junctions that have an annealing temperature of 200℃. The silicidation process was optimized by measuring the electrical characteristics of the Ni-silicided Schottky diodes. As a result, the Ion/Ioff current ratio is about 1.4×10⁵ and the subthreshold swing and field effect mobility are 0.42 V/dec and 14 cm²/V·s at a drain voltage of −1 V, respectively.

• E2M - 전기 전자와 첨단 소재
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• 제8권1호
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• pp.56-63
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• 1995

MESFETs of the Ti/Au and Ti/Pd/Au gate were fabricated on n-type GaAs. Interdiffusion at Schottky interfaces, Schottky contact properties, and MESFET characteristics with heat treatment were investigated. Ti of Ti/Au contact and Pd of Ti/Pd/Au contact acted as a barrier metal against interdiffusion of Au at >$220^{\circ}C$. Pd of Ti/Pd/Au contact acted as a barrier metal even at >$360^{\circ}C$, however, Ti of Ti/Au contact promoted interdiffusion of Au instead of role of barrier metal. As the heat treatment temperature increases, in the case of both contact, saturated drain current and pinch off voltage decreased, open channel resistance increased, and degree of parameter variation in Ti/Au gate was higher than in Ti/Pd/Au gate at >$360^{\circ}C$ Schottky barrier height of Ti/Au and Ti/Pd/Au contacts was 0.69eV and 0.68eV in the as-deposited state, respectively, and Fermi level was pinned in the vicinity of 1/2Eg. As the heat treatment temperature increases, barrier height of Ti/Pd/Au contact increased, however, decreased at >$360^{\circ}C$ in the case of Ti/Au contact. Ideality factor of Ti/Au contact was nearly constant regardless of heat treatment, however, increased at >$360^{\circ}C$ in the case of Ti/Au contact. From the results above, Ti/Pd/Au was stable gate metal than Ti/Au.