• ETRI Journal
• /
• v.34 no.6
• /
• pp.950-953
• /
• 2012

Schottky barrier single electron transistors (SB-SETs) and Schottky barrier single hole transistors (SB-SHTs) are fabricated on a 20-nm thin silicon-on-insulator substrate incorporating e-beam lithography and a conventional CMOS process technique. Erbium- and platinum-silicide are used as the source and drain material for the SB-SET and SB-SHT, respectively. The manufactured SB-SET and SB-SHT show typical transistor behavior at room temperature with a high drive current of $550{\mu}A/{\mu}m$ and $-376{\mu}A/{\mu}m$, respectively. At 7 K, these devices show SET and SHT characteristics. For the SB-SHT case, the oscillation period is 0.22 V, and the estimated quantum dot size is 16.8 nm. The transconductance is $0.05{\mu}S$ and $1.2{\mu}S$ for the SB-SET and SB-SHT, respectively. In the SB-SET and SB-SHT, a high transconductance can be easily achieved as the silicided electrode eliminates a parasitic resistance. Moreover, the SB-SET and SB-SHT can be operated as a conventional field-effect transistor (FET) and SET/SHT depending on the bias conditions, which is very promising for SET/FET hybrid applications. This work is the first report on the successful operations of SET/SHT in Schottky barrier devices.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.5
• /
• pp.572-578
• /
• 2014

In order to overcome small current drivability of a tunneling field-effect transistor (TFET), a TFET using Schottky barrier (SBTFET) is proposed. The proposed device has a metal source region unlike the conventional TFET. In addition, dopant segregation technology between the source and channel region is applied to reduce tunneling resistance. For TFET fabrication, spacer technique is adopted to enable self-aligned process because the SBTFET consists of source and drain with different types. Also the control device which has a doped source region is made to compare the electrical characteristics with those of the SBTFET. From the measured results, the SBTFET shows better on/off switching property than the control device. The observed drive current is larger than those of the previously reported TFET. Also, short-channel effects (SCEs) are investigated through the comparison of electrical characteristics between the long- and short-channel SBTFET.

• Journal of the Semiconductor & Display Technology
• /
• v.5 no.1 s.14
• /
• pp.21-25
• /
• 2006

To improve the performance of organic thin film transistor, we investigated the properties of gate insulator's surface according to the leakage current by I-V measurement. The surface was treated by the dilute n-octadecyltrichlorosilane solution. The alkyl group of n-octadecyltrichlorosilane induced the electron tunneling and the electron tunneling current caused the breakdown at high electric field, consequently shifting the breakdown voltage. The 0.5% sample with an electron-rich group was found to have a large leakage current and a low barrier height because of the effect of an energy barrier lowered by, thermionic current, which is called the Schottky contact. The surface properties of the insulator were analyzed by I-V measurement using the effect of Poole-Frankel emission.

• Journal of the Korean Vacuum Society
• /
• v.18 no.4
• /
• pp.302-309
• /
• 2009

We fabricated a Si nano floating gate memory with Schottky barrier tunneling transistor structure. The device was consisted of Schottky barriers of Er-silicide at source/drain and Si nanoclusters in the gate stack formed by LPCVD-digital gas feeding method. Transistor operations due to the Schottky barrier tunneling were observed under small gate bias < 2V. The nonvolatile memory properties were investigated by measuring the threshold voltage shift along the gate bias voltage and time. We obtained the 10/50 mseconds for write/erase times and the memory window of $\sim5V$ under ${\pm}20\;V$ write/erase voltages. However, the memory window decreased to 0.4V after 104seconds, which was attributed to the Er-related defects in the tunneling oxide layer. Good write/erase endurance was maintained until $10^3$ write/erase times. However, the threshold voltages moved upward, and the memory window became small after more write/erase operations. Defects in the LPCVD control oxide were discussed for the endurance results. The experimental results point to the possibility of a Si nano floating gate memory with Schottky barrier tunneling transistor structure for Si nanoscale nonvolatile memory device.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.779-782
• /
• 2003

The theoretical and experimental current-voltage characteristics of Erbium silicided n-type Schottky barrier tunneling transistors (SBTTs) are discussed. The theoretical drain current to drain voltage characteristics show good correspondence and the extracted Schottky barrier height is 0.24 eV. The experimentally manufactured n-type SBTTs with 60 nm gate lengths show typical transistor behaviors in drain current to drain voltage characteristics. The drain current on/off ratio is about 10$^{5}$ at low drain voltage regime in drain current to gate voltage characteristics.

• Proceeding of EDISON Challenge
• /
• 2016.03a
• /
• pp.299-304
• /
• 2016

2차원 반도체 소재의 경우 물질종류마다 내포하고 있는 고유결함에 의해서 Fermi-Level Pinning 이 발생하여 이로 인한 Schottky Barrier transistor로 동작을 하게 되며, 이는 접합부에 Carrier Injection 정도와 Schottky Barrier을 통과하는 Tunneling 정도에 의해서 소자의 특성이 결정 된다. 본 연구에서는 시뮬레이션을 통하여 2차원 반도체인 $MoS_2$소자를 설계하고, S/D Doping에 따라 접촉 저항 개선 효과와 소자의 동작특성이 어떠한 영향을 미치는지 연구하여 최대 $250cm^2/V{\cdot}sec$의 field effect mobility 의 결과를 얻었다. 또한 S/D doping 에 따라 각 저항 성분의 영향을 분석하였으며 면저항 및 접촉 저항 둘 다 doping 농도가 증가함에 따라 감소하는 결과를 나타내며, S/D doping의 영향은 접촉저항에서 더 크게 나타났다. 더불어 2차원 반도체의 Resistance network model 을 제안하여 subthreshold 영역에서는 $R_{ic}$, saturation 영역에서는 $R_{ish}$ 가 전체저항에서 주요한 변수로 전체저항식에 포함되어야 한다는 것을 시뮬레이션을 통해서 검증하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.29 no.3
• /
• pp.147-151
• /
• 2016

Graphene has a monolayer crystal structure formed with C-atoms and has been used as a base layer of HETs (hot electron transistors). Graphene HETs have exhibited the operation at THz frequencies and higher current on/off ratio than that of Graphene FETs. In this article, we report on the preliminary results of current characteristics from the HETs which are fabricated utilizing highly doped Si collector, graphene base, and 5 nm thin $Al_2O_3$ tunnel layers between the base and Ti emitter. We have observed E-B forward currents are inherited to tunneling through $Al_2O_3$ layers, but have not noticed the Schottky barrier blocking effect on B-C forward current at the base/collector interface. At the common-emitter configuration, under a constant $V_{BE}$ between 0~1.2V, $I_C$ has increased linearly with $V_{CE}$ for $V_{CE}$ < $V_{BE}$ indicating the saturation region. As the $V_{CE}$ increases further, a plateau of $I_C$ vs. $V_{CE}$ has appeared slightly at $V_{CE}{\simeq}V_{BE}$, denoting forward-active region. With further increase of $V_{CE}$, $I_C$ has kept increasing probably due to tunneling through thin Schottky barrier between B/C. Thus the current on/off ration has exhibited to be 50. To improve hot electron effects, we propose the usage of low doped Si substrate, insertion of barrier layer between B/C, or substrates with low electron affinity.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2007.08a
• /
• pp.307-307
• /
• 2007