• The Transactions of the Korea Information Processing Society
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• v.7 no.10
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• pp.3226-3235
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• 2000

The more complex and larger semiconductor integraed circuits become, the core important delay test becomes which guarantees that semiconductor integrated circuits operate in time. In this paper, we propose a new partial enhanced scan method that can generate test patterns for path delay faults offectively. We implemented a new partial enhanced scan method based on an automatic test pattern generator(ATPG) which uses implication and justification . First. we generate test patterns in the standard scan environment. And if test patterns are not generated regularly in the scan chain, we determine flip-flops which applied enhanced scan flip-flops using the information derived for running an automatic test pattern generator inthe circuti. Determming enhanced scan flip-flops are based on a fault coverage or a hardware overhead. through the expenment for JSCAS 89 benchmark sequential circuits, we compared the fault coverage in the standard scan enviroment and enhance scan environment, partial enhanced scan environment. And we proved the effectiveness of the new partial enhanced scan method by identifying a high fault coverage.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1840-1841
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• 2007

To the Boundary Scan, this architecture in Scan testing of design under the control of boundary scan is used in boundary scan design to support the internal scan chain. The internal scan chain has single scan-in port and single scan-out port that multiple scan chain cannot be used. Internal scan design has multiple scan chains, those chains must be stitched to form a scan chain as this paper. We propose an efficient Boundary Scan test structure for multiple clock testing in design.

• Journal of Veterinary Clinics
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• v.35 no.3
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• pp.93-96
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• 2018

This study aimed to establish an injection protocol to determine the precise CT scan timing in canine abdominal multi-phase CT using the test bolus method. Three dynamic scans with different contrast injection parameters were performed using a crossover design in eight normal beagle dogs. A contrast material was administered at a fixed dose of 200 mg iodine/kg as a test bolus for dynamic scans 1 and 2, and 600 mg iodine/kg as a main bolus for dynamic scan 3. The contrast materials were administered with 1 ml/s in dynamic scan 1, and 3 ml/s in dynamic scan 2 and 3. The mean arrival time to the appearance of aortic enhancement in dynamic scan 3 was similar to that in dynamic scan 2, and different significantly to that in dynamic scan 1. The mean arrival time to the peak aortic and pancreatic parenchymal enhancement in dynamic scan 3 was similar to that in dynamic scan 1, and different significantly to that in dynamic scan 2. In multi-phase CT scan, a test bolus should be injected with the same injection duration of a main bolus, to obtain the precise arrival times to peak of arterial or pancreatic parenchymal enhancement.

• The Journal of Korean Academy of Prosthodontics
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• v.42 no.1
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• pp.1-10
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• 2004

Statement of problem : Tooth wear is physiological phenomenon. Ninety-seven percent of normal people have tooth wear and about 7% has pathologic teeth wear. If we know the amount of tooth surface loss caused by pathologic tooth wear, we may restore it ideally Purpose : Recently measurement of tooth wear by using 3D scan has been increasing. Therefore, we need to know how accurate 3D scan is. Past accuracy test on 3D scan was about linear change, but as we know that tooth wear is volume change. Thus, the purpose of this study is to know how accurate 3D scan is. Material and Methods : For accuracy test of 3D scanner volume values measured by 3D scanner and micro-balance were compared. For test I, preliminary, 3 ball samples and 3 circular cones were made with pattern resin. For test II, 10 teeth shape rubber samples were used. Results and Conclusion : 1. The result of the accuracy test on 3D scan with 3 ball samples and 3 circular cones made of pattern resin has no significant difference(p<0.05). 2. The result of the accuracy test on 3D scan with 10 samples of tooth shape rubber has no significant difference (p<0.05). As a result, we may concluded the analysis of quantifying tooth wear used by 3D scan is useful in the clinic.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.4
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• pp.219-225
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• 2014

The New efficient Mux-based scan latch cell design and scan test of LOS/LOC modes are proposed for detection of delay faults in digital logic circuits. The proposed scan cell design can support LOS(Launch-off-Shift) and LOC(Launch-off-Capture) tests with high fault coverage and low scan power and it can alleviate the problem of the slow selector enable signal and hold signal by supporting the logic capable of switching at the operational clock speeds. Also, it efficiently controls the power dissipation of the scan cell design during scan testing. Functional operation and timing simulation waveform for proposed scan hold cell design shows improvement in at-speed test timing in both test modes.

• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.669-671
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• 1998

Due to the serial nature of scan chains, the use of the boundary scan chain leads the high application costs. And with 3-state net, it is important to avoid enabling the two drivers in a net. In this paper, the new test method for 3-state nets in the multiple boundary scan chains is presented. This method configures the boundary scan cells as multiple scan chains and the test application time can be reduced. Also three efficient algorithms are proposed for testing the interconnects in a board without the collision of the test data in 3-state nets.

• Journal of Electrical Engineering and Technology
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• v.4 no.4
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• pp.559-565
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• 2009

Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. The high switching activity of combinational circuits is an unnecessary operation in scan shift mode. In this paper, we present a novel architecture to reduce test power dissipation in combinational logic by blocking signal transitions at the logic inputs during scan shifting. We propose a unique architecture that uses dmuxed scan flip-flop (DSF) and transmission gate as an alternative to muxed scan flip-flop. The proposed method does not have problems with auto test pattern generation (ATPG) techniques such as test application time and computational complexity. Moreover, our elegant method improves performance degradation and large overhead in terms of area with blocking logic techniques. Experimental results on ITC99 benchmarks show that the proposed architecture can achieve an average improvement of 30.31% in switching activity compared to conventional scan methods. Additionally, the results of simulation with DSF indicate that the powerdelay product (PDP) and area overhead are improved by 28.9% and 15.6%, respectively, compared to existing blocking logic method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.640-648
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• 2014

Excessive power dissipation is one of the major issues in the testing of VLSI systems. Many techniques are proposed for scan test, but there are not so many for logic BIST because of its unmanageable randomness. This paper presents a novel low switching activity BIST scheme that reduces toggle frequency in the majority of scan chain inputs while allowing a small portion of scan chains to receive pseudorandom test data. Reducing toggle frequency in the scan chain inputs can reduce test power but may result in fault coverage loss. Allowing a small portion of scan chains to receive pseudorandom test data can make better uniform distribution of 0 and 1 and improve test effectiveness significantly. When compared with existing methods, experimental results on larger benchmark circuits of ISCAS'89 show that the proposed strategy can not only reduce significantly switching activity in circuits under test but also achieve high fault coverage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.85-97
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• 2002

STUMPS has been widely used for built-in self-test of scan design with multiple scan chains. In the STUMPS architecture, there is very high correlation between the bit sequences in the adjacent scan chains. This correlation causes circuits lower the fault coverage. In order to solve this problem, an extra combinational circuit block(phase shifter) is placed between the LFSR and the inputs of STUMPS architecture despite the hardware overhead increase. This paper introduces an efficient test pattern generation technique and built-in self-test architecture for sequential circuits with multiple scan chains. The proposed test pattern generator is not used the input of LFSR and phase shifter, hence hardware overhead can be reduced and sufficiently high fault coverage is obtained. Only several XOR gates in each scan chain are required to modify the circuit for the scan BIST, so that the design is very simple.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.70-76
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• 2015

This paper introduces an FPGA self-test architecture reusing FPGA boundary scan chain as self-test circuits. An FPGA boundary scan cell is two or three times bigger than a normal boundary scan cell because it is used for configuring the function of input/output pins functions as well as testing and debugging. Accordingly, we analyze the architecture of an FPGA boundary scan cell in detail and design a set of built-in self-test (BIST) circuits in which FPGA boundary scan chain and a small amount of FPGA logic elements. By reusing FPGA boundary scan chain for self-test, we can reduce area overhead and perform a processor based on-board FPGA testing/monitoring. Experimental results show the area overhead comparison and simulation results.