• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.70-76
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• 2015

This paper introduces an FPGA self-test architecture reusing FPGA boundary scan chain as self-test circuits. An FPGA boundary scan cell is two or three times bigger than a normal boundary scan cell because it is used for configuring the function of input/output pins functions as well as testing and debugging. Accordingly, we analyze the architecture of an FPGA boundary scan cell in detail and design a set of built-in self-test (BIST) circuits in which FPGA boundary scan chain and a small amount of FPGA logic elements. By reusing FPGA boundary scan chain for self-test, we can reduce area overhead and perform a processor based on-board FPGA testing/monitoring. Experimental results show the area overhead comparison and simulation results.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.12
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• pp.142-150
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• 1996

Nowadays, as the development paeiod of new products becomes even shorter, the importance of Rapid Prototyping Technology(RPT) has been rapidly increased. The major application of RPT is an early verification of product designs and quick production of prototypes for testing. Moreover, RPT is applied not only as a second tooling process such as mold making and investment casting but also as a creating some physical structure in medical field. Despite the remarkable progress of RPT, it is required to improve various problems resulting from application such as production time, accuracy and materials. This paper presents a laser scan path generation for accuracy of stereolithographicparts The methodology of laser scan path generation is discussed based on the stereolithography, The procedure of this research is as follows : 1) Input laser scanning conditions such as a laser beam diameter and a laser scanning interval, 2) Reconstruct original contours without self intersecting offset, 3) Calculate offset about reconstructed contours, 4) Calculate intersection points between horizontal or vertical lines and offset contours for internal hatch, 5) Decide laser shutter on/off points. The algorithm developed and programmed by C language is verified as an efficient method after testing a number of STL files of mechanical parts.

• Journal of the Korean Society for Nondestructive Testing
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• v.37 no.2
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• pp.84-90
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• 2017

An ultrasonic synthetic aperture focusing technique (SAFT) using a root mean square (RMS) velocity model is proposed for pulse-echo immersion testing to improve the computational efficiency. Considering the immersion ultrasonic testing of a steel block as an example, three kinds of imaging were studied (B-Scan, SAFT imaging based on ray tracing technology and RMS velocity). The experimental results show that two kinds of SAFT imaging have almost the same imaging performance, while the efficiency of RMS velocity SAFT imaging is almost 25 times greater than the SAFT based on Snell's law.

• Journal of the Korean Society for Nondestructive Testing
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• v.13 no.3
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• pp.7-13
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• 1993

Fracture behavior of pre-cracked compact tension specimens made of AISI 4130 steel was investigated using acoustic emission (AE) and ultrasonic C-scan measurements. While each specimen was loaded up to a certain level, various acoustic emission parameters were recorded together with the crack opening displacement (COD). An elastic-plastic finite element analysis was performed to calculate COD and the damage (plastic) zone size ahead of crack tip. Ultrasonic C-scans, in a pulse-echo, immersion mode, were done for mapping the damage zone size. The agreement between the finite element results and the measured COD was satisfactory. Based on AE results, the test specimens were found to show ductile behavior. The slope of the total ringdown counts vs. COD curve was useful to determine the crack initiation. The preliminary C-scan images showed evidence of changes in the amplitude of ultrasonic signal in the damaged region, and the shape and size of the damage zone matched qualitatively with the finite element results. A further work on the damage zone sizing was also pointed out.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.4
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• pp.219-225
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• 2014

The New efficient Mux-based scan latch cell design and scan test of LOS/LOC modes are proposed for detection of delay faults in digital logic circuits. The proposed scan cell design can support LOS(Launch-off-Shift) and LOC(Launch-off-Capture) tests with high fault coverage and low scan power and it can alleviate the problem of the slow selector enable signal and hold signal by supporting the logic capable of switching at the operational clock speeds. Also, it efficiently controls the power dissipation of the scan cell design during scan testing. Functional operation and timing simulation waveform for proposed scan hold cell design shows improvement in at-speed test timing in both test modes.

• The Transactions of the Korea Information Processing Society
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• v.7 no.10
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• pp.3226-3235
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• 2000

The more complex and larger semiconductor integraed circuits become, the core important delay test becomes which guarantees that semiconductor integrated circuits operate in time. In this paper, we propose a new partial enhanced scan method that can generate test patterns for path delay faults offectively. We implemented a new partial enhanced scan method based on an automatic test pattern generator(ATPG) which uses implication and justification . First. we generate test patterns in the standard scan environment. And if test patterns are not generated regularly in the scan chain, we determine flip-flops which applied enhanced scan flip-flops using the information derived for running an automatic test pattern generator inthe circuti. Determming enhanced scan flip-flops are based on a fault coverage or a hardware overhead. through the expenment for JSCAS 89 benchmark sequential circuits, we compared the fault coverage in the standard scan enviroment and enhance scan environment, partial enhanced scan environment. And we proved the effectiveness of the new partial enhanced scan method by identifying a high fault coverage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.79-90
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• 2005

In this paper, we propose a new clustered reconfigurable interconnect network (CRIN) BIST to improve the embedding probabilities of random-pattern-resistant-patterns. The proposed method uses a scan-cell reordering technique based on the signal probabilities of given test cubes and specific hardware blocks that increases the embedding probabilities of care bit clustered scan chain test cubes. We have developed a simulated annealing based algorithm that maximizes the embedding probabilities of scan chain test cubes to reorder scan cells, and an iterative algorithm for synthesizing the CRIN hardware. Experimental results demonstrate that the proposed CRIN BIST technique achieves complete fault coverage with lower storage requirement and shorter testing time in comparison with the conventional methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.83-90
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• 2004

This paper proposes an efficient scan testing method for compression of test input data and reduction of test power for SOC. The proposed method determines whether some parts of a test response can be reused as a part of next input test data on the analysis of deterministic test data and its response. Our experimental results show that benchmark circuits have a high similarity between un-compacted deterministic input test data and its response. The proposed testing method achieves the average of 29.4% reduction of power dissipation based on the number of test clock and 69.7% reduction of test data for ISCAS'89 benchmark circuits.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.2
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• pp.201-206
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• 2007

In this paper, we propose the efficient low power test methodology of NoC(Network-on chip) for the test of core-based systems that use this platform. To reduce the power consumption of transferring data through router channel, the scan vectors are partitioned into flits by channel width. The don't cares in unspecified scan vectors are mapped to binary values to minimize the switching rate between flits. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method leads to about 35% reduction in test power.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.199-208
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• 1994

This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.