• Journal of the Korean Institute of Intelligent Systems
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• v.24 no.5
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• pp.457-461
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• 2014

Using $0.18{\mu}m$ CMOS process silicon neuron circuit of the pulse type for modeling biological neurons, were designed in the semiconductor integrated circuit. Neuron circuiSt providing is formed by MOS switch for initializing the input terminal of the capacitor to the input current signal, a pulse signal and an amplifier stage for generating an output voltage signal. Synapse circuit that can convert the current signal output of the input voltage signal, using a bump circuit consisting of NMOS transistors and PMOS few. Configure a chain of neurons for verification of the neuron model that provides synaptic neurons and two are connected in series, were performed SPICE simulation. Result of simulation, it was confirmed the normal operation of the synaptic transmission characteristics of the signal generation of nerve cells.

• The KIPS Transactions:PartC
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• v.12C no.7 s.103
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• pp.989-998
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• 2005

Information systems are today becoming larger and mostly broadband-networked. This exposes them at a higher risk of intrusions and hacking than ever before. Of the technologies developed to meet information system security needs, risk analysis is currently one of the most actively researched areas. Meanwhile, due to the extreme diversity of assets and complexity of network structure, there is a limit to the level of accuracy which can be achieved by an analysis tool in the assessment of risk run by an information system. Also, the results of a risk assessment are most oftennot up-to-date due to the changing nature of security threats. By the time an evaluation and associated set of solutions are ready, the nature and level of vulnerabilities and threats have evolved and increased, making them obsolete. Accordingly, what is needed is a risk analysis tool capable of assessing threats and propagation of damage, at the same time as security solutions are being identified. To do that, the information system must be simplified, and intrusion data must be diagrammed using a modeling technique this paper, we propose a modeling technique information systems to enable security risk analysis, using SPICE and Petri-net, and conduct simulations of risk analysis on a number of case studies.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.1138-1143
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• 2015

Effects of fabrication process variations on impedance of microelectrodes integrated on a neural probe were examined through equivalent circuit modeling and SPICE simulation. Process variation and the corresponding range were estimated based on experimental data. The modeling results illustrate that the process variation induced by metal etching process was the dominant factor in impedance variation. We also demonstrate that the effect of process variation is frequency dependent. Another process variation that was examined in this work was the thickness variation induced by deposition process. The modeling results indicate that the effect of thickness variation on impedance is negligible. This work provides a means to predict the variations in impedance values of microelectrodes on neural probe due to different process variations.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.447-450
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• 2004

The modeling circuit becomes more important in developing various magnetic devices regarding the fact that the competitive architecture and circuitry should be developed simultaneously. In this paper, we introduce a modeling circuit for hysteresis characteristic of a magnetic device, which is a major characteristic in the spin dependent magnetic material. This transistor-level model is conspicuous in that it can be usefully embodied in real circuits rather than conventional SPICE models are only for simulations.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.206-219
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• 1996

This paper describes a data structure and evaluation algorithm to improve the perofmrances MOS logic-with-timing simulation in computation and accuracy. In order to efficiently simulate the logic and timing of driver-load networks, (1) a tree data structure to represent the mutual interconnection topology of switches and nodes in the driver-lod network, and (2) an algebraic modeling to efficiently deal with the new represetnation, (3) an evaluation algorithm to compute the linear resistive and capacitive behavior with the new modeling of driver-load networks are developed. The higher modeling presented here supports the structural and functional compatibility with the linear switch-level to simulate the logic-with-timing of digital MOS circuits at a mixed-level. This research attempts to integrate the new approach into the existing simulator RSIM, which yield a mixed-klevel logic-with-timing simulator MIXIM. The experimental results show that (1) MIXIM is a far superior to RSIM in computation speed and timing accuracy; and notably (2) th etiming simulation for driver-load netowrks produces the accuracy ranged within 17% with respect ot the analog simulator SPICE.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.201-204
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• 2001

In this paper, for modeling of electrical characteristics in Poly Silicon Thin Film Transistors with process parameters set up optimum values, So, the I-V characteristics of poly silicon TFT parameters are examined and simulated in terms of the variations in process parameter. And these results compared and analyzed simulation values with examination value. The simulation program for characteristic analysis used SUPREM IV for processing, Matlab for modeling by mathematics, and SPICE for electric characteristic of devices. Input parameter for simulation characteristics is like condition of device process sequence, these electric characteristic of $I_D-V_D$ $I_D-V_G$, variations of grain size. The Gate oxide thickness of poly silicon are showed similar results between real device characteristics and simulation characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.201-204
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• 2001

In this paper, for modeling of electrical characteristics in Poly Silicon Thin Film Transistors with process parameters set up optimum values. So, the I-V characteristics of poly silicon TFT parameters are examined and simulated in terms of the variations in process parameter. And these results compared and analyzed simulation values with examination value. The simulation program for characteristic analysis used SUPREM IV for processing, Matlab for modeling by mathematics, and SPICE for electric characteristic of devices. Input parameter for simulation characteristics is like condition of device process sequence, these electric characteristic of I$_{D}$-V$_{D}$, I$_{D}$-V$_{G}$, variations of grain size. The Gate oxide thickness of poly silicon are showed similar results between real device characteristics and simulation characteristics.ristics.

• Journal of the Semiconductor & Display Technology
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• v.16 no.3
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• pp.59-64
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• 2017

As the demand on displays increases, new thin-film transistors such as metal oxide transistor are continuously being invented. When designing a circuit consisting of such new transistors, a new transistor model based on proper charge transport mechanisms is needed for each of them. In this paper, a modeling framework which enables to choose charge transport mechanisms that are limited to certain operation regions and assemble them into a transistor model instead of making an integrated transistor model dedicated to each transistor. The framework consists of a graphic user interface to choose charge transport models and a current calculation part, which is also implemented in AIM-SPICE for circuit simulation.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.5
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• pp.531-539
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• 1991

We develop an analytical model of the static and the dynamic characteristics of amorphous silicon thin film transistors (a-Si TFTs) in order to incorporate into a widely used circuit simulator such as SPICE. The critical parameters considered in our analytical model of a-Si TFT are the power factor (XN) of saturation source-drain current and the effective channel length (L') at saturation region. The power factor, XN must not always obey so-called

• Journal of Sensor Science and Technology
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• v.14 no.2
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• pp.96-100
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• 2005

The planar Schottky diodes were fabricated and modeled to probe the device applicability of the cracked GaN epitaxial layer on a (111) silicon substrate. On the unintentionally n-doped GaN grown on silicon, we deposited Ti/Al/Ni/Au as the ohmic metal and Pt as the Schottky metal. The ohmic contact achieved a minimum contact resistivity of $5.51{\times}10.5{\Omega}{\cdot}cm^{2}$ after annealing in an $N_{2}$ ambient at $700^{\circ}C$ for 30 sec. The fabricated Schottky diode exhibited the barrier height of 0.7 eV and the ideality factor was 2.4, which are significantly lower than those parameters of crack free one. But in photoresponse measurement, the diode showed the peak responsivity of 0.097 A/W at 300 nm, the cutoff at 360 nm, and UV/visible rejection ratio of about $10^{2}$. The SPICE(Simulation Program with Integrated Circuit Emphasis) simulation with a proposed model, which was composed with one Pt/GaN diode and three parasitic diodes, showed good agreement with the experiment.