• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.331-331
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• 2012

With the NAND Flash scaling down, it becomes more and more difficult to follow Moore's law to continue the scaling due to physical limitations. Recently, three-dimensional (3D) flash memories have introduced as an ideal solution for ultra-high-density data storage. In 3D flash memory, as the process reason, we need to use poly-Si TFTs instead of conventional transistors. So, after combining charge trap flash (CTF) structure and poly-Si TFTs, the emerging device SONOS-TFTs has also suffered from some reliability problem such as hot carrier degradation, charge-trapping-induced parasitic capacitance and resistance which both create interface traps. Charge pumping method is a useful tool to investigate the degradation phenomenon related to interface trap creation. However, the curves for charge pumping current in SONOS TFTs were far from ideal, which previously due to the fabrication process or some unknown traps. It needs an optimization and the important geometrical effect should be eliminated. In spite of its importance, it is still not deeply studied. In our work, base-level sweep model was applied in SONOS TFTs, and the nonideal charge pumping current was optimized by adjusting the gate pulse transition time. As a result, after the optimizing, an improved charge pumping current curve is obtained.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.117-120
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• 2005

The SONOS devices have been fabricated by the conventional $0.35{\mu}m$ complementary metal-oxide-semiconductor (CMOS) process with NOR array. Two-bit operation using conventional process achieve the high density memory compare with other two-bit memory. Lateral diffusion phenomenon in the two-bit operation cause soft error in the memory. In this study, the programming conditions arc investigated in order to reduce lateral diffusion for two-bit operation of CSL-NOR type SONOS flash cell.

• 한국전기전자재료학회논문지
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• 제23권6호
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• pp.449-453
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• 2010

In this paper, the electrical characteristics of Fin-type SONOS(silicon-oxide-nitride-oxide-silicon) flash memory device with different trapping layers are analyzed in depth. Two kinds of trapping layers i.e., silicon nitride($Si_3N_4$) and hafnium oxide($HfO_2$) are applied. Compared to the conventional Fin-type SONOS device using the $Si_3N_4$ trapping layer, the Fin-type SOHOS(silicon-oxide-high-k-oxide-silicon) device using the $HfO_2$ trapping layer shows superior program/erase speed. However, the data retention properties in SOHOS device are worse than the SONOS flash memory device. Degraded data retention in the SOHOS device may be attributed to the tunneling leakage current induced by interface trap states, which are supported by the subthreshold slope and low frequency noise characteristics.

• 전자공학회논문지
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• 제49권10호
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• pp.111-121
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• 2012

본 연구에서는 $0.5{\mu}m$ 급 다결정 실리콘 박막 트랜지스터를 제작하고 이를 최적화 했다. 실험 결과, 비정질 실리콘을 증착 후 저온 어닐링을 통해 보다 큰 grain 크기를 가지는 active 영역을 형성하는 것이 소자의 SS(Subthreshold Swing), DIBL(Drain Induced Barrier Lowering), 그리고 on-current의 성능 향상을 가져온다는 것을 확인 할 수 있었다. 또한 이를 바탕으로 SONOS 플래시 메모리를 제작하였으며 그 특성을 분석했다. 게이트로부터 전자의 back tunneling 현상을 억제함과 동시에 제작한 소자가 원활한 program/erase 동작을 하기 위해서는 O/N/O 두께의 최적화가 필요하다. 따라서 시뮬레이션을 통해 이를 분석하고 O/N/O 두께를 최적화 하여 SONOS 플래시 메모리의 특성을 개선하였다. 제작한 소자는 2.24 V의 threshold voltage($V_{th}$) memory window를 보였으며 메모리 동작을 잘 하는 것을 확인 할 수 있었다.

• Transactions on Electrical and Electronic Materials
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• 제14권5호
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• pp.250-253
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• 2013

In this paper, we fabricated 3D pillar type silicon-oxide-nitride-oxide-silicon (SONOS) devices for high density flash applications. To solve the limitation between erase speed and data retention of the conventional SONOS devices, bandgap-engineered (BE) tunneling oxide of oxide-nitride-oxide configuration is integrated with the 3D structure. In addition, the tunneling oxide is modulated by another method of $N_2$ ion implantation ($N_2$ I/I). The measured data shows that the BE-SONOS device has better electrical characteristics, such as a lower threshold voltage ($V_{\tau}$) of 0.13 V, and a higher $g_{m.max}$ of 18.6 ${\mu}A/V$ and mobility of 27.02 $cm^2/Vs$ than the conventional and $N_2$ I/I SONOS devices. Memory characteristics show that the modulated tunneling oxide devices have fast erase speed. Among the devices, the BE-SONOS device has faster program/erase (P/E) speed, and more stable endurance characteristics, than conventional and $N_2$ I/I devices. From the flicker noise analysis, however, the BE-SONOS device seems to have more interface traps between the tunneling oxide and silicon substrate, which should be considered in designing the process conditions. Finally, 3D structures, such as the pillar type BE-SONOS device, are more suitable for next generation memory devices than other modulated tunneling oxide devices.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.469-472
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• 2004

In this paper a current mode sense amplifier suitable for 30nm SONOS flash memories read operation is presented. The proposed sense amplifier employs cross coupled latch type circuit and current mirror to amplify signal from selected memory cell. This sense amplifier provides fast response in low voltage and low current dissipation. Simulation results show the sensing delay time and current dissipation for power supply voltages Vdd to expose limitations of the sense amplifier in various operating conditions.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.37-40
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• 2004

SONOS를 이용한 전하트랩형 플래시 메모리를 통상의 0.35um CMOS 공정을 이용하여 제작하였으며 그 구조는 소스를 공통(CSL. Common Source Line)으로 사용하는 NOR형으로 하였다. 기존의 공정을 그대로 이용하면서 멀티 비트 동작을 통한 실질적 집적도 향상을 얻을 수 있다면 그 의미가 크다고 하겠다. 따라서 본 연구에서는CSL-NOR형 플래시 구조에서 멀티 비트을 구현하기위한 최적의 프로그램/소거/읽기 전압 조건을 구하여 국소적으로 트랩된 전하의 분포를 전하펌핑 방법을 이용하여 조사하였다. 또한 이 방법을 이용하여 멀티 비트 동작 시 문제점으로 제시된 전하의 측면확산을 측정하였다.

• Transactions on Electrical and Electronic Materials
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• 제11권4호
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• pp.155-165
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• 2010

As a promising candidate to replace the conventional floating gate flash memories, polysilicon-oxide-nitride-oxidesilicon (SONOS)-type nonvolatile semiconductor memories have been investigated widely in the past several years. SONOS-type memories have some advantages over the conventional floating gate flash memories, such as lower operating voltage, excellent endurance and compatibility with standard complementary metal-oxide-semiconductor (CMOS) technology. However, their operating speed and date retention characteristics are still the bottlenecks to limit the applications of SONOS-type memories. Recently, various approaches have been used to make a trade-off between the operating speed and the date retention characteristics. Application of high-k dielectrics to SONOS-type memories is a predominant route. This article provides the state-of-the-art research progress of high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories. It begins with a short description of working mechanism of SONOS-type memories, and then deals with the materials' requirements of high-k dielectrics used for SONOS-type memories. In the following section, the microstructures of high-k dielectrics used as tunneling layers, charge trapping layers and blocking layers in SONOS-type memories, and their impacts on the memory behaviors are critically reviewed. The improvement of the memory characteristics by using multilayered structures, including multilayered tunneling layer or multilayered charge trapping layer are also discussed. Finally, this review is concluded with our perspectives towards the future researches on the high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.119-119
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• 2008

The electrical characteristics of Metal-Ferroelectric-Nitride-Oxide-Silicon (MFNOS) structure is studied and compared to the conventional Silicon-Oixde-Nitride-Oxide-Silicon (SONOS) capacitor. The ferroelectric blocking layer is SrBiNbO (SBN with Sr/Bi ratio 1-x/2+x) with the thickness of 200 nm and is fabricated by the RF sputter. The memory windows of MFNOS and SONOS capacitors with sweep voltage from +10 V to -10 V are 6.9 V and 5.9 V, respectively. The effect of ferroelectric blocking layer and charge trapping on the memory window was discussed. The retention of MFNOS capacitor also shows the 10-years and longer retention time than that of the SONOS capacitor. The better retention properties of the MFNOS capacitor may be attributed to the charge holding effect by the polarization of ferroelectric layer.

• 한국전기전자재료학회논문지
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• 제18권3호
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• pp.193-198
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• 2005

NOR type flash 32 ${\times}$ 32 way are fabricated by using the typical 0.35 ${\mu}{\textrm}{m}$ CMOS process. The structure of array is the NOR type with common source line. In this paper, optimized program and erase voltage conditions are presented to realize multi-bit per cell at the CSL-NOR array. These are considered selectivity of selected bit and disturbances of unselected bits. Retention characteristics of locally trapped-charges in the nitride layer are investigated. The lateral diffusion and vertical detrapping to the tunneling oxide of locally trapped charges as a function of retention time are investigated by using the charge pumping method. The results are directly shown by change of the trapped-charges quantities.