Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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The Optimization of $0.5{\mu}m$ SONOS Flash Memory with Polycrystalline Silicon Thin Film Transistor

다결정 실리콘 박막 트랜지스터를 이용한 $0.5{\mu}m$ 급 SONOS 플래시 메모리 소자의 개발 및 최적화

  • Kim, Sang Wan (Department of Electrical Engineering and Computer Science, Seoul National University) ;
  • Seo, Chang-Su (Inter-University Semiconductor Research Center (ISRC), Seoul National University) ;
  • Park, Yu-Kyung (Inter-University Semiconductor Research Center (ISRC), Seoul National University) ;
  • Jee, Sang-Yeop (Inter-University Semiconductor Research Center (ISRC), Seoul National University) ;
  • Kim, Yun-Bin (Inter-University Semiconductor Research Center (ISRC), Seoul National University) ;
  • Jung, Suk-Jin (Inter-University Semiconductor Research Center (ISRC), Seoul National University) ;
  • Jeong, Min-Kyu (Department of Electrical Engineering and Computer Science, Seoul National University) ;
  • Lee, Jong-Ho (Department of Electrical Engineering and Computer Science, Seoul National University) ;
  • Shin, Hyungcheol (Department of Electrical Engineering and Computer Science, Seoul National University) ;
  • Park, Byung-Gook (Department of Electrical Engineering and Computer Science, Seoul National University) ;
  • Hwang, Cheol Seong (Department of Materials Science and Engineering, Seoul National University)
  • 김상완 (서울대학교 전기.컴퓨터공학부) ;
  • 서창수 (서울대학교 반도체공동연구소) ;
  • 박유경 (서울대학교 반도체공동연구소) ;
  • 지상엽 (서울대학교 반도체공동연구소) ;
  • 김윤빈 (서울대학교 반도체공동연구소) ;
  • 정숙진 (서울대학교 반도체공동연구소) ;
  • 정민규 (서울대학교 전기.컴퓨터공학부) ;
  • 이종호 (서울대학교 전기.컴퓨터공학부) ;
  • 신형철 (서울대학교 전기.컴퓨터공학부) ;
  • 박병국 (서울대학교 전기.컴퓨터공학부) ;
  • 황철성 (서울대학교 재료공학부)
  • Received : 2012.07.10
  • Published : 2012.10.25
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Abstract

In this paper, a poly-Si thin film transistor with ${\sim}0.5{\mu}m$ gate length was fabricated and its electrical characteristics are optimized. From the results, it was verified that making active region with larger grain size using low temperature annealing is an efficient way to enhance the subthreshold swing, drain-induced barrier lowering and on-current characteristics. A SONOS flash memory was fabricated using this poly-Si channel process and its performances are analyzed. It was necessary to optimize O/N/O thickness for the reduction of electron back tunneling and the enhancement of its memory operation. The optimized device showed 2.24 V of threshold voltage memory windows which coincided with a well operating flash memory.

본 연구에서는 $0.5{\mu}m$ 급 다결정 실리콘 박막 트랜지스터를 제작하고 이를 최적화 했다. 실험 결과, 비정질 실리콘을 증착 후 저온 어닐링을 통해 보다 큰 grain 크기를 가지는 active 영역을 형성하는 것이 소자의 SS(Subthreshold Swing), DIBL(Drain Induced Barrier Lowering), 그리고 on-current의 성능 향상을 가져온다는 것을 확인 할 수 있었다. 또한 이를 바탕으로 SONOS 플래시 메모리를 제작하였으며 그 특성을 분석했다. 게이트로부터 전자의 back tunneling 현상을 억제함과 동시에 제작한 소자가 원활한 program/erase 동작을 하기 위해서는 O/N/O 두께의 최적화가 필요하다. 따라서 시뮬레이션을 통해 이를 분석하고 O/N/O 두께를 최적화 하여 SONOS 플래시 메모리의 특성을 개선하였다. 제작한 소자는 2.24 V의 threshold voltage($V_{th}$) memory window를 보였으며 메모리 동작을 잘 하는 것을 확인 할 수 있었다.

Keywords

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