• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.100-106
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• 1999

A new IBC(Island Body Contact) structure is introduced to SOI CMOS VLSI for stabilizing the body potential of the MOSFET without the additional area consumption. The improvement of the body contact effect is achieved by reducing the body resistance and the area is saved as the bodies of the MOSFETs are connected together. Its property as VLSI device is confirmed through the device simulations and the measurement.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.3
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• pp.83-88
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• 2003

The optoelectronic characteristics of semiconducto-atomic superlattice as a function of deposition temperature and annealing conditions have been studied. The nanocrystalline silicon/adsorbed oxygen superlattice formed by molecular beam epitaxy(MBE) system. As an experimental result, the superlattice with multilayer Si-O structure showed a stable photoluminescence(PL) and good insulating behavior with high breakdown voltage. This is very useful promise for Si-based optoelectronics and quantum devices as well as for the replacement of silicon-on-insulator (SOI) in ultra-high speed and lower power CMOS devices in the future, and it can be directly integrated with silicon ULSI processing.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.12
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• pp.2010-2015
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• 1989

A SOI was fabricated by the FIPOS technique using n/p+/p silicon structure. Fabricated silicon island which has 3\ulcorner thickness and 100\ulcorner width was investigated by measuring van der Pauw resistivity, Hall mobility, dielectric breakdown voltage and leakage current. Hall mobility of the SOI was measured to be 300-500cm\ulcornerV.sec and its breakdown field was 1-2 MV/cm. The cross-sectional geometries of the SOI island were examined by SEM and optical microscope.

• 전자공학회논문지 IE
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• v.47 no.1
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• pp.1-5
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• 2010

This paper presents new results of the impact of gate structure on hot-carrier-induced performance degradation in SOI low noise amplifier. Circuit simulations were carried out using the measured S-parameters of H--gate and T-gate SOI MOSFETs and Agilent's Advanced Design System (ADS) to compare the performance of H-gate LNA and T-gate LNA before and after stress. We will discuss the figure of merit for the characterization of low noise amplifier in terms of impedance matching (S11), noise figure, and gain as well as the relation between device degradation and performance degradation of LNA.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.3
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• pp.228-233
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• 2001

This paper presents the optimized design, fabrication and thermal characteristics of micro-heaters for thermal MEMS (micro elelctro mechanical system) applications usign SOI (Si-on-insulator) and trench structures. The micro-heater is based on a thermal measurement principle and contains for thermal isolation regions a 10㎛ thick Si membrane with oxide-filled trenches in the SOI membrane rim. The micro-heater was fabricated with Pt-RTD (resistance thermometer device) on the same substrate by suing MgO as medium layer. The thermal characteristics of the micro-heater wit the SOI membrane is 280$\^{C}$ at input power 0.9W; for the SOI membrane with 10 trenches, it is 580$\^{C}$ due to reduction of the external thermal loss. Therefore, the micro-heater with trenches in SOI membrane rim provides a powerful and versatile alternative technology for improving the performance of micro-thermal sensors and actuators.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.569-572
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• 2000

This paper presents the optimized fabrication and thermal characteristics of micro-heaters for thermal MEMS applications using a SDB SOI substrate. The micro-heater is based on a thermal measurement principle and contains for thermal isolation regions a 10$\mu\textrm{m}$ thick silicon membrane with oxide-filled trenches in the SOI membrane rim. The micro-heater was fabricated with Pt-RTD(Resistance Thermometer Device)on the same substrate by using MgO as medium layer. The thermal characteristics of the micro-heater with the SOI membrane is 280$^{\circ}C$ at input Power 0.9 W; for the SOI membrane with 10 trenches, it is 580$^{\circ}C$ due to reduction of the external thermal loss. Therefore, the micro-heater with trenches in SOI membrane rim provides a powerful and versatile alternative technology for improving the performance of micro thermal sensors and actuators.

• Proceedings of the KIEE Conference
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• 2002.11a
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• pp.159-160
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• 2002

본 논문에서는 반도체 응용부문 중 그 활용도가 높은 MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor)의 새로운 구조를 제안하였다. 제안한 소자를 가지고 전자회로의 구성할 때 인접 디바이스들과 연계되어 발생되는 래치 업(latch-up)을 근본적으로 제거하고, 개별소자의 완전한 절연을 실현하였으며 누설전류 또한 제거된다. 이는 SOI기판 위에 벌크실리콘 공정을 이용하여 구현된다. 즉, 소자 양옆의 트랜치 웰(Trench-well)과 SOI 기판의 절연층으로 소자의 독립성을 지켜준다. 또한 게이트 절연층을 트랜치 구조로 기존 MOS구조의 채널 부분에 위치시키고 드레인과 소스를 위치시켜 자연적으로 자기정렬이 되어진다. 이와 같은 과정으로 게이트-소스, 게이트-드레인 기생 커패시터의 효과를 현저히 줄일 수 있다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.6
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• pp.428-435
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• 1998

SOI-like-bulk CMOS device is proposed, which having the advantages of SOI(Silicon On Insulator) and protects short channel effects efficiently with adding partial epitaxial process at standard CMOS process. SOI-like-bulk NMOS and PMOS with 0.25${\mu}{\textrm}{m}$ gate length have designed and optimized through analyzing the characteristics of these devices and applying again to the design of processes. The threshold voltages of the designed NMOS and PMOS are 0.3[V], -0.35[V] respectively and those have shown the stable characteristics under 1.5[V] gate and drain voltages. The leakage current of typical bulk-CMOS increase with shortening the channel length, but the proposed structures on this a study reduce the leakage current and improve the subthreshold characteristics at the same time. In addition, subthreshold swing value, S is 70.91[mV/decade] in SOI-like-bulk NMOS and 63.37[mV/ decade] SOI-like-bulk PMOS. And the characteristics of SOI-like-bulk CMOS are better than those of standard bulk CMOS. To validate the circuit application, CMOS inverter circuit has designed and transient & DC transfer characteristics are analyzed with mixed mode simulation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.557-560
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• 2000

Combination of SDB(Si-wafer Direct Bonding) and electrochemical etch-stop in TMAH anisotropic etchant can be used to create a variety of MEMS(Micro Electro Mechanical System). Especially, fabrication of SDB SOI structures using electrochemical etch-stop is accurate method to fabrication of 3D(three-dimensional) microstructures. This paper describes on the fabrication of SDB SOI structures with sealed cavity for MEMS applications and thickness control of active layer on the SDB SOI structure by electrochemical etch-stop. The flatness of fabricated SDB SOI structure is very uniform and can be improved by addition of TMAH to IPA and pyrazine.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.163-166
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• 2003

The electrothermal simulation of high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) in thin Silicon on insulator (SOI) and Silicon on sapphire (SOS) for thermal conductivity and sink is performed by means of MEDICI. The finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on-insulator (SOI) devices. In this paper, using for SOI LIGBT, we simulated electrothermal for device that insulator layer with $SiO_2\;and\;Al_2O_3$ at before and after latch up to measured the thermal conductivity and temperature distribution of whole device and verified that SOI LIGBT with $Al_2O_3$ insulator had good thermal conductivity and reliability