• Journal of the Korea Society of Computer and Information
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• v.23 no.10
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• pp.111-117
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• 2018

CHAM is a lightweight block cipher, proposed in ICISC 2017. CHAM-n/k has the n-bit block and the k-bit key, and designers recommend CHAM-64/128, CHAM-128/128, and CHAM-128/256. In this paper, we study how to make optimal software implementation of CHAM such that it has high encryption speed on CPUs with high computing power. The best performances of our CHAM implementations are 1.6 cycles/byte for CHAM-64/128, 2.3 cycles/byte for CHAM-128/128, and 3.8 cycles/byte for CHAM-128/256. The comparison with existing software implementation results for well-known block ciphers shows that our results are competitive.

• Journal of Korea Multimedia Society
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• v.16 no.8
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• pp.914-926
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• 2013

Among the recent security systems, security system with fingerprint recognition gets many people's interests through the strengths such as exclusiveness, convenience, etc, in comparison with other security systems. The most important matters for fingerprint recognition system are reliability of matching between the fingerprint in database and user's fingerprint and rapid process of image processing algorithms used for fingerprint recognition. The existing fingerprint recognition system reduces the processing time by removing some processes in the feature extraction algorithms but has weakness of a reliability. This paper realizes the fingerprint recognition algorithm using MAMS(Multi-Access Memory System) for both the rapid processing time and the reliability in feature extraction and matching accuracy. Reliability of this process is verified by the correlation between serial processor's results and MAMS-PP64's results. The performance of the method using MAMS-PP64 is 1.56 times faster than compared serial processor.

• The Transactions of the Korea Information Processing Society
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• v.5 no.6
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• pp.1620-1632
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• 1998

This paper presents a fast parallel algorithm for volume rendering and its implementation using C language and MPI MasPar Programming Language) on the 4,096 processor MasPar MP-2 machine. This parallel algorithm is a parallelization hased on the Lacroute' s sequential shear - warp algorithm currently acknowledged to be the fastest sequential volume rendering algorithm. This algorithm reduces communication overheads by using the sheared space partition scheme and the load balancing technique using load estimates from the previous iteration, and the number of voxels to be processed by using the run-length encoded volume data structure.Actual performance is 3 to 4 frames/second on the human hrain scan dataset of $128\times128\times128$ voxels. Because of the scalability of this algorithm, performance of ]2-16 frames/sc.'cond is expected on the 16,384 processor MasPar MP-2 machine. It is expected that implementation on more current SIMD or MIMD architectures would provide 3O~60 frames/second on large volumes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.85-95
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• 2008

Characteristically, 3D graphic algorithms have to perform complex calculations on massive amount of stream data. The vertex and pixel shaders have enabled efficient execution of graphic algorithms by hardware, and these graphic processors may seem to have achieved the aim of "hardwarization of software shaders." However, the hardware shaders have hitherto been evolving within the limits of Z-buffer based algorithms. We predict that the ultimate model for future graphic processors will be an algorithm-independent integrated shader which combines the functions of both vertex and pixel shaders. We design the register file model that supports 3-dimensional computer graphic on the programmable unified shader processor. we have verified the accurate calculated value using FPGA Virtex-4(xcvlx200) made by Xilinx for operating binary files made by the implementation progress based on synthesis results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.56-70
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• 2010

Rendering technique generating 2 dimensional image to give reality and high performance graphical processor for efficient processing of massive data are necessary to support realistic 3 dimensional graphical image. Recently, graphical hardwares have evolved rapidly. This enables high quality rendering effect that we were unable to process in realtime. Improving shading technique enabled us to render realistic images but still much time is required for this process. Multiple operational units are being integrated in a graphical processor for effective floating point operation using massive data to process almost real looking images. In this paper, we have designed and implemented a special functional unit to support high quality 3 dimensional computer graphic image on programmable integrated shader processor. We have done evaluation through functional level simulation of designed special functional unit. Hardware resource usage rate and execution speed are measured implementing directly on FPGA Virtex-4(xc4vlx200).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.66-73
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• 2002

As floating-point operations become widely used in various applications such as computer graphics and high-definition DSP, the needs for fast division become increased. However, conventional floating-point dividers occupy a large hardware area, and bring bottle-becks to the entire floating-point operations. In this paper, a high-performance and small-area floating-point divider, which is suitable for embedded processors, is designed using he series expansion algorithm. The algorithm is selected to utilize two MAC(Multiply-ACcumulate) units for quadratic convergence to the correct quotient. The two MAC units for SIMD-DSP features are shared and the additional area for the division only is very small. The proposed divider supports all rounding modes defined by IEEE 754 standard, and error estimations are performed for appropriate precision.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.5
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• pp.487-492
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• 2018

Recently, various applications for image processing have been ported to the mobile environment due to the expansion of the image shooting on the mobile device. However, in the case of extracting the image foreground, which is one of the most important functions of image synthesis, is difficult since it needs complex calculation. In this paper, we propose an video synthesis technique that can divide images captured by mobile devices into foreground / background and combine them in real time on target images. Considering the characteristics of mobile shooting, our system can extract automatically foreground of input video that contains weak motion when shooting. Using SIMD and GPGPU-based acceleration algorithms, SD-quality images can be processed on mobile in real time.

• Journal of the Korea Society of Computer and Information
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• v.17 no.1
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• pp.1-10
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• 2012

Improving operating frequency of processors is no longer today's issues; a multiprocessor technique which integrates many processors has received increasing attention. Currently, high-performance processors that integrate 64 or 128 cores are developing for large data processing over 2, 4, or 8 processor cores. This paper proposes an optimal many-core processor for synthesizing guitar sounds. Unlike the previous research in which a processing element (PE) was assigned to support one of guitar strings, this paper evaluates the impacts of mapping different numbers of PEs to one guitar string in terms of performance and both area and energy efficiencies using architectural and workload simulations. Experimental results show that the maximum area energy efficiencies were achieved at PEs=24 and 96, respectively, for synthesizing guitar sounds with sampling rate of 44.1kHz and 16-bit quantization. The synthesized sounds were very similar to original guitar sounds in their spectra. In addition, the proposed many-core processor was 1,235 and 22 times better than TI TMS320C6416 in area and energy efficiencies, respectively.

• Smart Media Journal
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• v.10 no.3
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• pp.31-38
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• 2021

It is hard to predict when and where a fall accident will happen. Also, if rapid follow-up measures on it are not performed, a fall accident leads to a threat of life, so studies that can automatically detect a fall accident have become necessary. Among automatic fall-accident detection techniques, a fall detection scheme using an IMU (inertial measurement unit) sensor attached to a wrist is difficult to detect a fall accident due to its movement, but it is recognized as a technique that is easy to wear and has excellent accessibility. To overcome the difficulty in obtaining fall data, this study proposes an algorithm that efficiently learns less data through machine learning such as KNN (k-nearest neighbors) and SVM (support vector machine). In addition, to improve the performance of these mathematical classifiers, this study utilized feature data aquired in the frequency space. The proposed algorithm analyzed the effect by diversifying the parameters of the model and the parameters of the frequency feature extractor through experiments using standard datasets. The proposed algorithm could adequately cope with a realistic problem that fall data are difficult to obtain. Because it is lighter than other classifiers, this algorithm was also easy to implement in small embedded systems where SIMD (single instruction multiple data) processing devices were difficult to mount.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1141-1144
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• 2005

일반 컴퓨터에서 중앙처리장치와 메모리 사이의 병목 현상인 "Von Neumann Bottleneck"을 보이는데 본 논문에서는 이러한 문제점을 해소하고 검색위주의 응용분야에서 우수한 성능을 보이는 확장 가능한 범용 Associative Processor(AP) 구조를 제안하였다. 본 연구에서는 Associative computing을 효율적으로 수행할 수 있는 명령어 세트를 제안하였으며 다양하고 대용량 응용분야에도 적용할 수 있도록 구조를 확장 가능하게 설계함으로써 유연한 구조를 갖는다. 12 가지의 명령어가 정의되었으며 프로그램이 효율적으로 수행될 수 있도록 명령어 셋을 구성하고 연속된 명령어를 하나의 명령어로 구현함으로써 처리시간을 단축하였다. 제안된 프로세서는 bit-serial, word-parallel로 동작하며 대용량 병렬 SIMD 구조를 갖는 32 비트 범용 병렬 프로세서로 동작한다. 포괄적인 검증을 위하여 명령어 단위의 검증 뿐 아니라 최대/최소 검색, 이상/이하 검색, 병렬 덧셈 등의 기본적인 병렬 알고리즘을 검증하였으며 알고리즘은 처리 데이터의 개수와는 무관한 상수의 복잡도 O(k)를 갖으며 데이터의 비트 수만큼의 이터레이션을 갖는다.