• Proceedings of the Korean Society of Computer Information Conference
• /
• 2023.07a
• /
• pp.95-97
• /
• 2023

본 논문에서는 임베디드 기반의 다양한 센서를 활용한 드론의 비행기록장치 시스템 개발에 대한 새로운 아이디어를 제시한다. 이 시스템은 오픈소스 기반의 개발 보드인 라즈베리파이를 중심으로, 온도, 습도, 조도, 미세먼지 센서, 이산화탄소, 일산화탄소, 산소, 이산화질소, 아황산가스, 메탄가스, GPS, 고도 측정, IR 카메라, 카메라 모듈 센서 등 다양한 센서를 탑재하여 구성한다. 기존 드론은 주로 방역 및 방제 활동에 활용되었으나, 그 활동의 효과를 정밀하게 측정하고 분석하는 데에는 한계가 있었다. 그러나 이 논문에서 제안하는 임베디드 기반의 센서 구성은 이러한 한계를 극복할 수 있을 것으로 기대된다.

• Journal of IKEEE
• /
• v.17 no.3
• /
• pp.275-283
• /
• 2013

In this paper, a 8bit 10Ms/s CMOS Folding and Interpolation analog-to-digital convertor is proposed. The architecture of the proposed ADC is based on a Folding & Interpolation using FR(Folding Rate)=8, NFB(Number of Folding Block)=4, IR(Interpolation Rate)=8. The proposed ADC adopts a preamplifier sharing method to decrease the number of preamplifier by half comparing to the conventional ones. This chip has been fabricated with a 0.35[um] CMOS technology. The effective chip area is $1.8[mm]{\times}2.11[mm]$ and it consumes 20[mA] at 3.3 power supply with 10[MHz] clock. The INL is -0.57, +0.61 [LSB] and DNL is -0.4, +0.51 [LSB]. The SFDR is 48.9[dB] and SNDR is 47.9[dB](ENOB 7.6b) when the input frequency is 100[kHz] at 10[MHz] conversion rate.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.5
• /
• pp.67-74
• /
• 2013

A low-power 12-bit resistor string DAC for wireless sensor applications is presented. Two-step approach reduces complexity, minimizes power consumption and area, and increases speed. This chip is fabricated in 0.18-${\mu}m$ CMOS and the die area is $0.76mm{\times}0.56mm$. The measured power consumption is 1.8mW from the supply voltage of 1.8V. Measured SFDR(Spurious-Free Dynamic Range) is 70dB when the sampling frequency is less than 1 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.1
• /
• pp.47-55
• /
• 2005

This work describes an 8b 240 MS/s CMOS ADC as one of embedded core cells for high-performance displays requiring low power and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipelined architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip I/V references to improve noise performance with a power-off function added for portable applications. The prototype ADC is implemented in a 0.18 um CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The measured DNL and INL are within 0.49 LSB and 0.69 LSB, respectively. The prototype ADC shows the SFDR of 53 dB for a 10 MHz input sinewave at 240 MS/s while maintaining the SNDR exceeding 38 dB and the SFDR exceeding 50 dB for input frequencies up to the Nyquist frequency at 240 MS/s. The ADC consumes, 104 mW at 240 MS/s and the active die area is 1.36 ㎟.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.1
• /
• pp.92-97
• /
• 2009

Low power consumption is crucial for medical implantable devices. A low-power 4th-order band-pass Gm-C filter with distributed gain stage for the sensing stage of the implantable cardiac pacemaker is proposed. For the implementation of large-time constants, a floating-gate operational transconductance amplifier with current division is employed. Experimental results for the filter have shown a SFDR of 50 dB. The power consumption is below $1.8{\mu}W$, the power supply is 1.5 V, and the core area is $2.4\;mm{\times}1.3\;mm$. The filter was fabricated in a 1-poly 4-metal $0.35-{\mu}m$ CMOS process.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.63 no.3
• /
• pp.371-375
• /
• 2014

In this paper, we compared the performances of the Right Handed Transmission Line (RHTL) and the Left Handed Transmission Line (LHTL) phase shifters as a frequency translator. Unlike other phase shifters, both phase shifters show a $0^{\circ}-360^{\circ}$ phase variation for a broadband frequency and compact in size which are ideal to use as a frequency translator. For the performance comparison, we fabricated both a RHTL and a LHTL phase shifter to cover 1.5 GHz - 2.4 GHz range with the whole $360^{\circ}$ phase variation. For the frequency range, a LHTL based frequency translator showed a much better performance whose Spurious Free Dynamic Range (SFDR) is 4dB - 17dB higher than the RHTL based frequency translator when the sawtooth modulation freqncy is 11 kHz. This is due to the linear phase-voltage variation of LHTL phase shifter. Furthermore, the LHTL phase shifter shows a less insertion loss and a insertion loss variation than the RHTL phase shifter. Overall, the LHTL based frequency translator outperformed RHTL based freqency translator.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.12 no.2
• /
• pp.267-272
• /
• 2017

In this paper, we suggested that a RF-front module of down-converter that represents the lowest noise figure to receive high quality video signals because the attenuation occurs in the atmosphere over 20GHz. By budget analysis of CDR, SFDR and CIP3 of RF-FEM, we also analyzed the parameters and linearity that presents high dynamic range. The total gain of designed Ka-band down-converter is 61.8dBand noise figure is 1.05dB, so gain and noise figures show excellent properties. In the future, the designed RF-FEM will be applied to the Ka-band satellite down-converter for UHD-class video transmission.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.6
• /
• pp.18-24
• /
• 2012

This paper reports the test results of a 50MHz/s 10 bits DAC developed with $0.18{\mu}m$ CMOS process for the wireless sensor network application. The 10bits DAC, not likely a typical segmented type, has been designed as a current driving type with double step thermometer decoding architecture in which 10bits are divided into 6bits of MSB and 4bits of LSB. MSB 6bits are converted into 3 bits row thermal codes and 3 bits column thermal codes to control high current cells, and LSB 4 bits are also converted into thermal codes to control the lower current cells. The high and the lower current cells use the same cell size while a bias circuit has been designed to make the amount of lower unit current become 1/16 of high unit current. All thermal codes are synchronized with output latches to prevent glitches on the output signals. The test results show that the DAC consumes 4.3mA DC current with 3.3V DC supply for 2.2Vpp output at 50MHz clock. The linearity characteristics of DAC are the maximum SFDR of 62.02dB, maximum DNL of 0.37 LSB, and maximum INL of 0.67 LSB.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.301-304
• /
• 1999

밀리미터파 대역의 아날로그 광전송을 위한 진행파형 (travel ing wave, TW) 전계흡수 광변조기 (electroabsorption modulator, EAM)와 광수신기의 설계에 대해 발표하고자 한다. TW EAM 및 TW 광수신기의 일반적인 형태인 ridge-type의 co-planar waveguide (CPW)구조에서의 마이크로파의 전송특성을 3차원 FDTD로 분석하여 광파와 전파의 속도 정합 등을 이루는 최적화 구조를 설계하였다. TW EAM의 경우 광세기 변조의 비선형 응답특성에 있어서 마이크로파 손실과 소자길이가 RF 신호의 혼변조 왜곡 (intermodulation distortion)과 SFDR (spurious free dynamic range)성능에 미치는 영향도 이론적으로 조사하였다. TW PIN 광수신기의 경우 광파와 마이크로파의 속도정합의 영향과 이전에는 고려되지 않았던 photo-generated 전송자의 진성 영역에서의 transit time이 광수신기의 밴드 폭에 미치는 영향을 분석하여 최적화 설계하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.8
• /
• pp.61-70
• /
• 2009

A 10b 30MS/s pipelined ADC operating under 1V power supply is presented. It utilizes a switched-RC based input sampling circuit and a resistive loop to reset the feedback capacitor in the multiplying digital-to-analog converter (MDAC) for the low-voltage operation. Cascaded switched-RC branches are used to achieve accurate grain of the MDAC for the first stage and separate switched-RC circuits are used in the sub-ADC to suppress the switching noise coupling to the MDAC input The measured differential and integral non-linearities of the prototype ADC fabricated in a 0.13${\mu}m$, CMOS process are less than 0.54LSB and 1.75LSB, respectively. The prototype ADC achieves 54.1dB SNDR and 70.4dB SFDR with 1V supply and 30MHz sampling frequency while consuming 17mW power.